Abstract A signal processing system (10) is described which has a processor (12), a random access memory (14) for storage of data, a read-only memory (16) for storage of both coefficients and instructions, and a selective cache memory (18) for storage of instructions that require high performance, and their associated buses. Instructions selected by the program are stored in the selective cache memory during their first call from the read only memory for use later in the program. An address sequencer (50) is described as one form of a control unit for executing the data stored in the selective cache memory. It generates a sequence of addresses repetitively, counts the number of iterations of the sequence of addresses, and informs the controller when a certain number of iterations have been completed. This creates a conditional branch statement in the program of the signal processing system (10).
A circuit for data processing with at least one primary memory for storing both instructions and coefficients in the form of data, wherein the improvement comprises: means for retrieving a set of data, including first and second subsets of data, from said primary memory; means for selecting said first subset of data from said set of data; a secondary memory for storing said first subset of data; means for retrieving concurrently said first subset from said secondary memory and said second subset from said primary memory, and control means for selectively executing said first stored subset of data with said second subset of data.
Claim 2
Dependent Claim
104 words
A circuit for data processing with at least one primary memory for storing both instructions and coefficients in the form of data, wherein the improvement comprises: means for retrieving a set of data, including first and second subsets of data, from said primary memory; means for selecting said first subset of data from said set of data; a secondary memory for storing said first subset of data; means for retrieving concurrently said first subset from said secondary memory and said second subset from said primary memory, and control means for selectively executing said first stored subset of data with said second subset of data.
Claim 3
Dependent Claim
65 words
The circuit of claim 1 wherein said control means comprises: means for repeatedly generating a sequence of addresses; means requiring zero lines of code for repeating a predetermined number of times an instruction set stored at said sequence of addresses; means for counting the iterations of said instruction set; and means for informing the control means when said predetermined number of iterations have been completed.