US5627993A
Expired / Lapsed
US
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Methods and systems for merging data during cache checking and write-back cycles for memory reads and writes
Assignee: GlobalFoundries Inc
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Filing: 1996-04-29
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Granted: 1997-05-06
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Expires: 2016-04-29
Abstract
Abstract Methods and system for memory control in a computer system having a store-in cache. In response to main memory read or write requests from a secondary processor, data is transferred into a buffer during a snoop cycle to the store-in cache. The data in the buffer is merged with write-back data from the store-in cache in a write operation. Data is provided directly from the buffer to the secondary processor and to main memory in a read operation. The buffer can be placed on a memory controller of the computer system. A second store-in cache can also be used for main memory transfers.
Inventors
- 👤 Richard P. Abato
- 👤 William R. Greer
- 👤 Christopher M. Herring
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 10:11
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0835
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
96 words
In a computer system having a main memory, a primary processor, a store-in cache for said primary processor, and a secondary processor, and wherein the computer system performs a plurality of write-back cycles, each write-back cycle updating the main memory with a data stream from said store-in cache, said data stream comprising data elements, a method for responding to a main memory write request from the secondary processor, said method comprising the step of: (a) inserting secondary processor data elements from the secondary processor into the data stream during at least one of the write-back cycles.
Claim 2
Dependent Claim
96 words
In a computer system having a main memory, a primary processor, a store-in cache for said primary processor, and a secondary processor, and wherein the computer system performs a plurality of write-back cycles, each write-back cycle updating the main memory with a data stream from said store-in cache, said data stream comprising data elements, a method for responding to a main memory write request from the secondary processor, said method comprising the step of: (a) inserting secondary processor data elements from the secondary processor into the data stream during at least one of the write-back cycles.
Claim 3
Dependent Claim
25 words
The method of claim 1, wherein the inserting step (a) includes the step of: (i) buffering the secondary processor data elements from the secondary processor.
Claim 4
Dependent Claim
59 words
The method of claim 2, wherein the computer system comprises a memory controller shared by the primary and secondary processors, the memory controller controlling access to the main memory, the memory controller including a buffer, and wherein the buffering step (i) includes; buffering the secondary processor data elements from the secondary processor in the buffer of the memory controller.
Claim 5
Dependent Claim
89 words
In a computer system having a main memory, a primary processor, a store-in cache for said primary processor, and a secondary processor, and wherein the computer system performs a plurality of write-back cycles, each write-back cycle updating the main memory with data from said store-in cache, a method for responding to a main memory read request from the secondary processor, said method comprising the step of: (a) transferring at least one data element from the store-in cache to the secondary processor during at least one of the write-back cycles.
Claim 6
Dependent Claim
89 words
In a computer system having a main memory, a primary processor, a store-in cache for said primary processor, and a secondary processor, and wherein the computer system performs a plurality of write-back cycles, each write-back cycle updating the main memory with data from said store-in cache, a method for responding to a main memory read request from the secondary processor, said method comprising the step of: (a) transferring at least one data element from the store-in cache to the secondary processor during at least one of the write-back cycles.
Claim 7
Dependent Claim
50 words
The method of claim 4, wherein the computer system comprises a buffer and wherein the transferring step (a) includes: (i) transferring the at least one data element from the store-in cache to the buffer; and (ii) transferring the at least one data element from the buffer to the secondary processor.
Claim 8
Dependent Claim
26 words
The method of claim 5, wherein the transferring step (a) further includes: (iii) transferring the at least one data element from the buffer to main memory.
Claim 9
Dependent Claim
51 words
The method of claim 4, wherein the computer system comprises a buffer and wherein the transferring step (a) includes: (i) transferring a second at least one data element from the store-in cache to the buffer; and (ii) transferring the second at least one data element from the buffer to main memory.
Claim 10
Dependent Claim
35 words
The method of claim 5, wherein the computer system comprises a memory controller shared by the primary and secondary processors, the memory controller controlling access to the main memory, the memory controller including said buffer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-05 | 2000-11-04 | 2001-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-05 | 2004-11-04 | 2005-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-05 | 2008-11-04 | 2009-05-06 | $7700.00 | Window Closed / Lapsed |