Superscalar instruction pipeline using alignment logic responsive to boundary identification logic for aligning and appending variable length instructions to instructions stored in cache

Claim 2

A superscaler instruction pipeline for a digital computer which supports self modifying code whereby a store to the instruction stream may occur in such a way that out of sequence execution will execute the modified instruction stream as if the store to the instruction stream operation had occurred in sequential program order and wherein instructions can be of variable length comprising: a memory storing said variable length instructions; a cache connected to said memory and responsive to an instruction fetch address for storing a subset of said instructions, boundaries of each of said instructions being marked in said cache by boundary fields; an instruction fetch unit connected to said cache for fetching instructions to be executed, said instruction fetch unit including an anticipation buffer loaded with sequentially anticipated prefetched instructions from said cache and a branch target instruction; a content addressable memory for storing an instruction address for each of a plurality of instructions; boundary identification logic operatively connected to said content addressable memory for identifying instruction boundaries for each of said plurality of instructions held in said cache, a next instruction in said anticipation buffer being located and identified by said boundary identification logic using said content addressable memory, said instruction fetch unit further including alignment logic connected to said anticipation buffer and responsive to said boundaries of instructions read from said cache for aligning and appending said anticipated prefetched instructions to said instructions held in said cache without first sequentially decoding said instruction; a dispatch unit connected to said instruction fetch unit for decoding and dispatching a plurality of instructions in a single cycle; a plurality of execution units connected to receive instructions from said dispatch unit and simultaneously executing respective ones of the instructions; a completion buffer connected to said plurality of execution units for temporarily storing results of executing instructions; a writeback unit connected to said completion buffer for writing back results to said cache; first logic means operatively connected to said content addressable memory for detecting an occurrence of a store to memory request to one of said instruction addresses; and second logic means responsive to the first logic means for controlling said writeback unit to delay the store to memory request until previous instructions are executed and then refetching instructions that follow the store to memory request in program order.

Claim 3

The superscaler instruction pipeline recited in claim 1 wherein said cache comprises an instruction cache and said instruction fetch unit comprises: a fetch buffer for holding instructions for decoding and dispatch by said dispatch unit; and a branch target anticipation cache containing a history table of branch target instructions, said alignment logic loading said fetch buffer with aligned instructions.

Claim 4

The superscaler instruction pipeline recited in claim 2 wherein each line in said instruction cache includes a byte with an associated boundary field which provides an indication of the nature of the byte, the boundary field marking the beginning of a variable length instruction and information about the instruction to reduce decode time, said boundary identification logic decoding said boundary field at a time when an instruction stored in an addressed cache line is fetched.

Claim 5

A superscalar instruction pipeline recited in claim 2, wherein said alignment logic comprises: a selector operatively connected to said anticipation buffer and said branch target anticipation cache; a left shift unit operatively connected to said selector; a merge unit operatively connected to said left shift unit; a right shift unit operatively connected to said merge unit; and a bypass operatively connected to said merge unit, wherein, said merge unit, said left shifter and said right shifter concatenate said instructions for decoding and dispatch, said bypass for transmitting said instructions for decoding and dispatch to said fetch buffer.

Claim 6

A superscalar instruction pipeline recited in claim 1, wherein said second logic means purges said instructions that follow the store to memory request prior to refetching said instructions that follow the store to memory request.

Claim 7

A superscalar instruction pipeline recited in claim 1, further comprising a branch history table for supplying speculative branch targets to said instruction fetch unit.

Claim 8

A superscalar instruction pipeline recited in claim 1, wherein said boundary identification logic includes means for identifying a type of instruction and means for writing said type of instruction in a memory location adjacent said instruction boundaries.

Claim 9

A superscalar instruction pipeline recited in claim 1, wherein said cache comprises at least one of multiple data cache units and multiple instruction cache units.

Claim 10

A superscaler instruction pipeline for a digital computer which supports self modifying code whereby a store to the instruction stream may occur in such a way that out of sequence execution will execute the modified instruction stream as if the store to the instruction stream operation had occurred in sequential program order and wherein instructions can be of variable length comprising: a memory storing said variable length instructions; a cache connected to said memory and responsive to an instruction fetch address for storing a subset of said instructions, boundaries of each of said instructions being marked in said cache by boundary fields; an instruction fetch unit connected to said cache for fetching instructions to be executed, said instruction fetch unit including an anticipation buffer loaded with sequentially anticipated prefetched instructions from said cache and a branch target instruction; a content addressable memory for storing an instruction address for each of a plurality of instructions; boundary identification logic operatively connected to said content addressable memory for identifying instruction boundaries for each of said plurality of instructions held in said cache, a next instruction in said anticipation buffer being located and identified by said boundary identification logic using said content addressable memory; a dispatch unit connected to said instruction fetch unit for decoding and dispatching a plurality of instructions in a single cycle; a plurality of execution units connected to receive instructions from said dispatch unit and simultaneously executing respective ones of the instructions; a completion buffer connected to said plurality of execution units for temporarily storing results of executing instructions; a writeback unit connected to said completion buffer for writing back results to said cache; first logic means operatively connected to said content addressable memory for detecting an occurrence of a store to memory request to one of said instruction addresses; and second logic means responsive to the first logic means for controlling said writeback unit to delay the store to memory request until previous instructions are executed and then refetching instructions that follow the store to memory request in program order, wherein said cache comprises an instruction cache and said instruction fetch unit comprises: a fetch buffer for holding instructions for decoding and dispatch by said dispatch unit; a branch target anticipation cache containing a history table of branch target instructions; and alignment logic connected to said anticipation buffer and branch target anticipation cache and responsive to said marked boundaries of instructions read from said instruction cache for aligning said instructions without first sequentially decoding said instructions, said alignment logic loading said fetch buffer with aligned instructions, wherein each line in said instruction cache includes a byte with an associated boundary field which provides an indication of the nature of the byte, the boundary field marking the beginning of a variable length instruction and information about the instruction to reduce decode time, said boundary identification logic decoding said boundary field at a time when an instruction stored in an addressed cache line is fetched, wherein the boundary field is a 2-bit field encoded as follows: 00=NOT A BOUNDARY 01=INSTRUCTION PREFIX BYTE 10=COMPLEX INSTRUCTION BOUNDARY (NO PREFIX) 11=SIMPLE INSTRUCTION BOUNDARY.

Claim 11

A superscaler instruction pipeline for a digital computer which supports self modifying code whereby a store to the instruction stream may occur in such a way that out of sequence execution will execute the modified instruction stream as if the store to the instruction stream operation had occurred in sequential program order and wherein instructions can be of variable length comprising: a memory storing said variable length instructions; a cache connected to said memory and responsive to an instruction fetch address for storing a subset of said instructions, boundaries of each of said instructions being marked in said cache by boundary fields; an instruction fetch unit connected to said cache for fetching instructions to be executed, said instruction fetch unit including an anticipation buffer loaded with sequentially anticipated prefetched instructions from said cache and a branch target instruction; a content addressable memory for storing an instruction address for each of a plurality of instructions; boundary identification logic operatively connected to said content addressable memory for identifying instruction boundaries for each of said plurality of instructions held in said cache, a next instruction in said anticipation buffer being located and identified by said boundary identification logic using said content addressable memory; a dispatch unit connected to said instruction fetch unit for decoding and dispatching a plurality of instructions in a single cycle; a plurality of execution units connected to receive instructions from said dispatch unit and simultaneously executing respective ones of the instructions; a completion buffer connected to said plurality of execution units for temporarily storing results of executing instructions; a writeback unit connected to said completion buffer for writing back results to said cache; first logic means operatively connected to said content addressable memory for detecting an occurrence of a store to memory request to one of said instruction addresses; and second logic means responsive to the first logic means for controlling said writeback unit to delay the store to memory request until previous instructions are executed and then refetching instructions that follow the store to memory request in program order, wherein said cache comprises an instruction cache and said instruction fetch unit comprises: a fetch buffer for holding instructions for decoding and dispatch by said dispatch unit; a branch target anticipation cache containing a history table of branch target instructions; and alignment logic connected to said anticipation buffer and branch target anticipation cache and responsive to said marked boundaries of instructions read from said instruction cache for aligning said instructions without first sequentially decoding said instructions, said alignment logic loading said fetch buffer with aligned instructions, wherein each line in said instruction cache includes a byte with an associated boundary field which provides an indication of the nature of the byte, the boundary field marking the beginning of a variable length instruction and information about the instruction to reduce decode time, said boundary identification logic decoding said boundary field at a time when an instruction stored in an addressed cache line is fetched, wherein the boundary field is a 2-bit field encoded as follows: 00=NOT A BOUNDARY 01=INSTRUCTION PREFIX BYTE 10=COMPLEX INSTRUCTION BOUNDARY (NO PREFIX) 11=SIMPLE INSTRUCTION BOUNDARY.

Claim 12

A superscaler instruction pipeline for a digital computer which supports self modifying code whereby a store to the instructions stream may occur in such a way that out of sequence execution will execute the modified instruction stream as if the store to the instruction stream operation had occurred in sequential program order, comprising: a first memory storing said instructions; a cache connected to said first memory for storing a subset of said instructions; an instruction fecth unit connected to said cache for fetching instructions to be executed, said instruction fetch unit including an anticipation buffer loaded with sequentially anticipated prefetched instructions from said cache and a branch target instruction; a second memory for storing a plurality of instruction addresses, each corresponding to one of said instructions to be executed; boundary identification logic operatively connected to said cache for identifying instruction boundries for each of said instructions held in said cache, a next instruction in said anticipation buffer located and identified by said boundary identification logic using said second memory, said instruction fetch unit further including alignment logic connected to said anticipation buffer and responsive to said boundaries of instructions read from said cache for aligning and appending said anticipated prefetched instructions to said instructions held in said cache without first sequentially decoding said instructions; means, operatively connected to said instruction fetch unit, for simultaneously executing at least two of said instructions to be executed; a writeback unit, connected to said means for simultaneously executing, for writing back results of said executing means to said cache in said sequential program order; means, operatively connected to said second memory, for detecting an occurrence of a store to memory request to a first memory location associated with said instruction addresses and for controlling said writeback unit to delay the store to memory request until previous instructions are executed, said detecting means then refetching instructions that follow the store to memory request in sequential program order.

Claim 13

A superscaler instruction pipeline for a digital computer which supports self modifying code whereby a store to the instructions stream may occur in such a way that out of sequence execution will execute the modified instruction stream as if the store to the instruction stream operation had occurred in sequential program order, comprising: a first memory storing said instructions; a cache connected to said first memory for storing a subset of said instructions; an instruction fecth unit connected to said cache for fetching instructions to be executed, said instruction fetch unit including an anticipation buffer loaded with sequentially anticipated prefetched instructions from said cache and a branch target instruction; a second memory for storing a plurality of instruction addresses, each corresponding to one of said instructions to be executed; boundary identification logic operatively connected to said cache for identifying instruction boundries for each of said instructions held in said cache, a next instruction in said anticipation buffer located and identified by said boundary identification logic using said second memory, said instruction fetch unit further including alignment logic connected to said anticipation buffer and responsive to said boundaries of instructions read from said cache for aligning and appending said anticipated prefetched instructions to said instructions held in said cache without first sequentially decoding said instructions; means, operatively connected to said instruction fetch unit, for simultaneously executing at least two of said instructions to be executed; a writeback unit, connected to said means for simultaneously executing, for writing back results of said executing means to said cache in said sequential program order; means, operatively connected to said second memory, for detecting an occurrence of a store to memory request to a first memory location associated with said instruction addresses and for controlling said writeback unit to delay the store to memory request until previous instructions are executed, said detecting means then refetching instructions that follow the store to memory request in sequential program order.

Claim 14

A superscalar instruction pipeline recited in claim 10, wherein instructions can be of variable length.

Claim 15

A superscalar instruction pipeline recited in claim 10, wherein said second memory comprises a content addressable memory.

Claim 16

A superscaler instruction pipeline recited in claim 10, wherein said boundary identification logic marks boundaries of each of said instructions in said cache with boundary fields.

Claim 17

A superscaler instruction pipeline recited in claim 13, wherein each line in said cache includes a byte associated with a boundary field of said boundary fields which provides an indication of a nature of the byte, the boundary field marking the beginning of an instruction of said instructions and containing information about the instruction to reduce decode time, said boundary identification logic decoding said boundary field at a time when an instruction stored in an addressed cache line is fetched.

Claim 18

A superscalar instruction pipeline recited in claim 10, wherein said execution means comprises: a dispatch unit connected to said instruction fetch unit for decoding and dispatching at least two of said instructions in a single cycle; a plurality of execution units connected to receive said instructions from said dispatch unit and simultaneously executing at least two of said instructions; and a completion buffer connected to said plurality of execution units for temporarily storing results of executing instructions.

Claim 19

A superscalar instruction pipeline recited in claim 10, wherein said instruction fetch unit includes an anticipation buffer loaded with sequentially anticipated prefetched instructions from said cache.

Claim 20

A superscaler instruction pipeline recited in claim 10, wherein said cache comprises an instruction cache and said instruction fetch unit comprises: a fetch buffer for holding instructions for decoding and dispatch by said dispatch unit; and a branch target anticipation cache containing a history table of branch target instructions, said alignment logic loading said fetch buffer with aligned instructions.

Claim 21

A superscalar instruction pipeline recited in claim 10, further comprising a branch history table for supplying speculative branch targets to said instruction fetch unit.

Claim 22

A superscalar instruction pipeline recited in claim 10, wherein said cache comprises at least one of multiple data cache units and multiple instruction cache units.

Claim 23

A superscalar instruction pipeline recited in claim 10, wherein said second logic means purges said instructions that follow the store to memory request prior to refetching said instructions that follow the store to memory request.