Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer

Claim 2

An instruction buffer system for a digital computer for controlling the delivery of instruction stream bytes between a memory and an instruction decoder, said instruction stream bytes being grouped together into variable length instructions, and said instruction decoder for decoding each of said bytes within said variable length instruction, the instruction buffer system comprising: an instruction buffer coupled between said memory and said instruction decoder and having multiple byte locations for receiving a first series of said instruction bytes, at least a portion of said first series of instruction bytes forming a variable length instruction to be decoded by said decoder first and second prefetch buffers for storing a preselected number of a second, subsequent series of bytes of instruction stream, means for delivering a shift signal responsive to the number of bytes of instruction stream contained in the variable length instruction currently being decoded by said decoder, a shifter for receiving said shift signal and shifting the contents of said instruction buffer by a preselected number of bytes responsive to said number of decoded bytes of instruction stream indicated by said shift signal, means for merging said shifted bytes with at least a portion of the contents of one of said first and second prefetch buffers, and delivering said merged bytes to said instruction buffer, means for refilling said first prefetch buffer with sequential bytes of said instruction stream when said first prefetch buffer is emptied, and means for refilling said second prefetch buffer with sequential bytes of said instruction stream when said second prefetch buffer is emptied.

Claim 3

An instruction buffer system, as set forth in claim 1, wherein the merging means includes means for retrieving a preselected number of sequential bytes of instruction stream from one of the first and second prefetch buffers and loading said preselected number of bytes into the buffer locations from which instruction stream bytes have been removed by the shifter, said preselected number of sequential bytes of instruction stream being responsive to said number of decoded bytes of instruction stream indicated by said shift signal.

Claim 4

An instruction buffer system, as set forth in claim 2, wherein the merging means includes means for receiving said sequential bytes of instruction stream retrieved from said first and second prefetch buffers and rotating the bytes by a preselected number of byte locations responsive to said number of bytes of instruction stream indicated by said shift signal before refilling said instruction buffer.

Claim 5

An instruction buffer system, as set forth in claim 1, wherein said means for refiling the first and second prefetch buffers refills the first and second prefetch buffers in response to the absence of said shift signal.

Claim 6

An instruction buffer system, as set forth in claim 1, including means for retrieving instruction stream bytes from the memory in response to both of said first and second prefetch buffers being empty of instruction stream bytes.

Claim 7

An instruction buffer system for a digital computer for controlling the delivery of instruction stream to an instruction decoder, said instruction stream being grouped into variable length instructions, and said instruction decoder for decoding each of said bytes within said variable length instruction, said instruction buffer system comprising: an instruction buffer having a plurality of storage locations for receiving a preselected number of the next sequential bytes of instruction stream desired by the decoder and delivering said preselected number of instruction stream bytes to said decoder; said instruction decoder for delivering a shift signal responsive to the number of bytes of the instruction stream located in the instruction buffer which are currently being decoded; first means for prefetching and maintaining in a first prefetch buffer a first preselected number of sequential bytes of the instruction stream; second means for prefetching and maintaining in a second prefetch buffer a second preselected number of sequential bytes of the instruction stream, said second preselected number of sequential bytes of the instruction stream being subsequent to the first preselected number of sequential bytes of the instruction stream; a shifter coupled to said instruction buffer and adapted for receiving said shift signal and shifting the bytes of said instruction buffer by a preselected number of storage locations responsive to said shift signal and delivering the shifted bytes to the instruction buffer; means for retrieving sequential bytes of the instruction stream from one of the first and second prefetch buffers and filling the instruction buffer storage locations from which bytes of the instruction stream have been removed by the shifter; means for refilling said first prefetch buffers with instruction stream bytes in response to said first prefetch buffers being emptied by said means for retrieving; and means for refilling said second prefetch buffer with instruction stream bytes in response to said second means being emptied by said means for retrieving.

Claim 8

An instruction buffer system for a digital computer for controlling the delivery of instruction stream to an instruction decoder, said instruction stream being grouped into variable length instructions, and said instruction decoder for decoding each of said bytes within said variable length instruction, said instruction buffer system comprising: an instruction buffer having a plurality of storage locations for receiving a preselected number of the next sequential bytes of instruction stream desired by the decoder and delivering said preselected number of instruction stream bytes to said decoder; said instruction decoder for delivering a shift signal responsive to the number of bytes of the instruction stream located in the instruction buffer which are currently being decoded; first means for prefetching and maintaining in a first prefetch buffer a first preselected number of sequential bytes of the instruction stream; second means for prefetching and maintaining in a second prefetch buffer a second preselected number of sequential bytes of the instruction stream, said second preselected number of sequential bytes of the instruction stream being subsequent to the first preselected number of sequential bytes of the instruction stream; a shifter coupled to said instruction buffer and adapted for receiving said shift signal and shifting the bytes of said instruction buffer by a preselected number of storage locations responsive to said shift signal and delivering the shifted bytes to the instruction buffer; means for retrieving sequential bytes of the instruction stream from one of the first and second prefetch buffers and filling the instruction buffer storage locations from which bytes of the instruction stream have been removed by the shifter; means for refilling said first prefetch buffers with instruction stream bytes in response to said first prefetch buffers being emptied by said means for retrieving; and means for refilling said second prefetch buffer with instruction stream bytes in response to said second means being emptied by said means for retrieving.

Claim 9

An instruction buffer system, as set forth in claim 6, wherein the instruction buffer refilling means includes means for receiving said sequential bytes of instruction stream retrieved from said first and second means and rotating the bytes by a preselected number of byte locations responsive to said shift signal before refilling said instruction buffer.

Claim 10

An instruction buffer system, as set forth in claim 6, wherein said means for refilling said first and second prefetch buffers refills said first and second prefetch buffers in response to the absence of said shift signal.

Claim 11

An instruction buffer system, as set forth in claim 6, wherein said means for retrieving includes means for retrieving instruction stream from a memory in response to said first and second prefetch buffers being empty.