US5625288A
Expired / Lapsed
US
⏱️ 0.0 years remaining
On-clip high frequency reliability and failure test structures
Assignee: National Technology and Engineering Solutions of Sandia LLC
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Filing: 1996-01-16
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Granted: 1997-04-29
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Expires: 2016-01-16
Abstract
Abstract Self-stressing test structures for realistic high frequency reliability characterizations. An on-chip high frequency oscillator, controlled by DC signals from off-chip, provides a range of high frequency pulses to test structures. The test structures provide information with regard to a variety of reliability failure mechanisms, including hot-carriers, electromigration, and oxide breakdown. The system is normally integrated at the wafer level to predict the failure mechanisms of the production integrated circuits on the same wafer.
Inventors
- 👤 Eric S. Snyder
- 👤 David V. Campbell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 03:53
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2855; G01R31/2856; G01R31/2858; G01R31/30
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
115 words
An on-chip reliability and failure testing system comprising: oscillator means for producing pulses at frequencies above about 100 kHz; external DC control means for the oscillator to control the frequency and duty cycle of the pulses and measure the output of a test structure means: and test structure means driven by the pulses from the oscillator means, said test structure means comprising at least one discreet microelectronic element dedicated solely to the testing system each of which element being configured so as to uniquely express a failure mechanism as it would occur in other functional microelectronic circuits on the chip that are not connected to the elements of the test system located on the chip.
Claim 2
Dependent Claim
115 words
An on-chip reliability and failure testing system comprising: oscillator means for producing pulses at frequencies above about 100 kHz; external DC control means for the oscillator to control the frequency and duty cycle of the pulses and measure the output of a test structure means: and test structure means driven by the pulses from the oscillator means, said test structure means comprising at least one discreet microelectronic element dedicated solely to the testing system each of which element being configured so as to uniquely express a failure mechanism as it would occur in other functional microelectronic circuits on the chip that are not connected to the elements of the test system located on the chip.
Claim 3
Dependent Claim
18 words
The system of claim 1 wherein the oscillator frequency is matched to the operating frequency of the chip.
Claim 4
Dependent Claim
15 words
The system of claim 1 further including on-chip heating means for the test structure means.
Claim 5
Dependent Claim
20 words
The system of claim 3 further including on-chip temperature sensing means for determining the temperature of the test structure means.
Claim 6
Dependent Claim
20 words
The system of claim 1 further including on-chip temperature sensing means for determining the temperature of the test structure means.
Claim 7
Dependent Claim
14 words
The system of claim 1 wherein the oscillator means is a voltage controlled oscillator.
Claim 8
Dependent Claim
14 words
The system of claim 1 wherein the oscillator means is a current controlled oscillator.
Claim 9
Dependent Claim
19 words
The system of claim 1 wherein the test structure means is adapted to test for hot carrier induced degradation.
Claim 10
Dependent Claim
19 words
The system of claim 8 wherein the test structure means comprises a device containing at least one MOS transistor.
Claim 11
Dependent Claim
19 words
The system of claim 8 wherein the test structure means comprises a device containing at least one bipolar transistor.
Claim 12
Dependent Claim
16 words
The system of claim 1 wherein the test structure means is adapted to test for electromigration.
Claim 13
Dependent Claim
14 words
The system of claim 11 wherein the test structure means comprises a metal line.
Claim 14
Dependent Claim
17 words
The system of claim 1 wherein the test structure means is adapted to test for oxide breakdown.
Claim 15
Dependent Claim
13 words
The system of claim 13 wherein the test structure means is a capacitor.
Claim 16
Dependent Claim
19 words
The system of claim 1 further comprising means to buffer and control the pulses to the test structure means.
Claim 17
Dependent Claim
48 words
The system of claim 1 wherein said external DC control means comprises means to terminate the application of pulses to the test structure means and means to measure the parameters of the test structure means in a state where they are not receiving pulses from the oscillator means.
Claim 18
Dependent Claim
92 words
An on-chip testing system comprising: oscillator means for producing pulses at frequencies above about 100 kHz; external DC control means for the oscillator to control the frequency of the pulses; test structure means driven by the pulses from the oscillator means; means to buffer and control the pulses to the test structure means; heating means for the test structure means; and temperature sensing means for determining the temperature of the test structure means and wherein said buffer means, temperature means and test structure means are connected to said external DC control means.
Claim 19
Dependent Claim
92 words
An on-chip testing system comprising: oscillator means for producing pulses at frequencies above about 100 kHz; external DC control means for the oscillator to control the frequency of the pulses; test structure means driven by the pulses from the oscillator means; means to buffer and control the pulses to the test structure means; heating means for the test structure means; and temperature sensing means for determining the temperature of the test structure means and wherein said buffer means, temperature means and test structure means are connected to said external DC control means.
Claim 20
Dependent Claim
14 words
The system of claim 17 wherein the oscillator means is a voltage controlled oscillator.
Claim 21
Dependent Claim
14 words
The system of claim 17 wherein the oscillator means is a current controlled oscillator.
Claim 22
Dependent Claim
48 words
The system of claim 17 wherein said external DC control means comprises means to terminate the application of pulses to the test structure means and means to measure the parameters of the test structure means in a state where they are not receiving pulses from the oscillator means.
Claim 23
Dependent Claim
20 words
The system of claim 17 wherein the test structure means comprise at least two separate test structures stressed in parallel.
Claim 24
Dependent Claim
31 words
The system of claim 21 wherein the test structure means are selected from the group consisting of hot carrier test structures, electromigration test structures, oxide integrity test structures, and combinations thereof.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-28 | 2000-10-28 | 2001-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-28 | 2004-10-28 | 2005-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-28 | 2008-10-28 | 2009-04-29 | $7700.00 | Window Closed / Lapsed |