US5099196A
Expired / Lapsed
US
⏱️ 0.0 years remaining
On-chip integrated circuit speed selection
Assignee: Dell USA LP
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Filing: 1990-11-09
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Granted: 1992-03-24
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Expires: 2010-11-09
Abstract
Abstract An electronic circuit for the detection of required operational speed of one or more integrated circuit semiconductor chips is used in conjunction with an off-the-shelf integrated circuit tester. The tester provides timing, control and a display. Each of the integrated circuit semiconductor chips is provided with a ring oscillator circuit for generating a series of pulses, timed by the tester for a fixed period of time. A counter, formed in each of the semiconductor chips counts the number of pulses generated during the fixed period of time. A number, generated in the tester, indicative of a required speed of operation is set in a latch assembly that is formed in each of the semiconductor chips. A comparator, also formed in each of the semiconductor chips, compares the contents of the latch with the contents of the counter and if the contents of the counter is equal to or larger than the contents of the latch, the tested semiconductor chip is acceptable. A display in the tester indicates the result. If the speed of operation is very high, then the number indicative of a required speed of operation is divided by, for example, two. The output of the oscillator is also divided by two so that the size of the counter and the latch is not exceeded.
Inventors
- 👤 Michael L. Longwell
- 👤 Terry J. Parks
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 10:50
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/30; G01R31/317; G01R31/3181; G01R31/319; G01R31/3193; G01R31/31937; G06; G06F; G06F2201/00; G06F2201/88
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
205 words
An electronic circuit for the detection of required operational speed of one or more integrated circuit semiconductor chips, in conjunction with an integrated circuit tester for providing timing, display, and control signal CLK, comprising: (a) an oscillator circuit, formed in each of the one or more semiconductor chips, for generating a series of pulses, timed by the tester, connected to time the oscillator for a fixed period of time; (b) a counter, connected to the oscillator and formed in each of the one or more semiconductor chips, for counting the number of pulses generated during the fixed period of time provided by the tester; (c) a store, formed in each of the one or more semiconductor chips, for holding a number indicative of a required speed of operation; and (d) a comparator, formed in each of the one or more semiconductor chips, for comparing the number indicative of a required speed of operation from the store with the number of pulses counted during the fixed period of time output to the display for indicating whether the number of pulses counted is equal to or greater than the number indicative of a required speed of operation, thereby identifying a chip having the required speed of operation.
Claim 2
Dependent Claim
205 words
An electronic circuit for the detection of required operational speed of one or more integrated circuit semiconductor chips, in conjunction with an integrated circuit tester for providing timing, display, and control signal CLK, comprising: (a) an oscillator circuit, formed in each of the one or more semiconductor chips, for generating a series of pulses, timed by the tester, connected to time the oscillator for a fixed period of time; (b) a counter, connected to the oscillator and formed in each of the one or more semiconductor chips, for counting the number of pulses generated during the fixed period of time provided by the tester; (c) a store, formed in each of the one or more semiconductor chips, for holding a number indicative of a required speed of operation; and (d) a comparator, formed in each of the one or more semiconductor chips, for comparing the number indicative of a required speed of operation from the store with the number of pulses counted during the fixed period of time output to the display for indicating whether the number of pulses counted is equal to or greater than the number indicative of a required speed of operation, thereby identifying a chip having the required speed of operation.
Claim 3
Dependent Claim
13 words
The circuit of claim 1 wherein the oscillator circuit comprises a ring oscillator.
Claim 4
Dependent Claim
11 words
The circuit of claim 2 wherein the counter comprises N stages.
Claim 5
Dependent Claim
11 words
The circuit of claim 3 wherein the store comprises latch means.
Claim 6
Dependent Claim
51 words
The circuit of claim 4 wherein the number indicative of a required speed is divided by a divisor before entry into the latch means, and further comprising a divider, for receiving the series of pulses from the ring oscillator counted during the fixed period of time and dividing by the divisor.
Claim 7
Dependent Claim
12 words
The circuit of claim 5 wherein the latch means comprises N latches.
Claim 8
Dependent Claim
11 words
The circuit of claim 6 wherein the comparator comprises N stages.
Claim 9
Dependent Claim
7 words
The circuit of claim 7 wherein N=7.
Claim 10
Dependent Claim
8 words
The circuit of claim 8 wherein the divisor=2.
Claim 11
Dependent Claim
25 words
The circuit of claim 9 wherein the oscillator is activated by the assertion of signal CLK, and is deactivated by the deassertion of signal CLK.
Claim 12
Independent Claim
128 words
A method of detecting required operational speed of one or more integrated circuit semiconductor chips, employing a chip tester for providing test timing and for displaying results, comprising the steps of: (a) forming an oscillator, counter, latch and comparator on each of the one or more integrated circuit semiconductor chips; (b) entering a number indicative of a required speed of operation into the latch; (c) starting the oscillator; (d) counting the oscillator pulses during the test timing provided by the tester; (e) comparing the number of counted oscillator pulses with the number indicative of a required speed of operation from the latch; and (f) accepting the chip when the number of counted oscillator pulses equals or is greater than the number indicative of a required speed of operation.
Claim 13
Independent Claim
128 words
A method of detecting required operational speed of one or more integrated circuit semiconductor chips, employing a chip tester for providing test timing and for displaying results, comprising the steps of: (a) forming an oscillator, counter, latch and comparator on each of the one or more integrated circuit semiconductor chips; (b) entering a number indicative of a required speed of operation into the latch; (c) starting the oscillator; (d) counting the oscillator pulses during the test timing provided by the tester; (e) comparing the number of counted oscillator pulses with the number indicative of a required speed of operation from the latch; and (f) accepting the chip when the number of counted oscillator pulses equals or is greater than the number indicative of a required speed of operation.
Claim 14
Dependent Claim
28 words
The method of claim 11 further comprising, after the step of comparing, the steps of: sending the result of comparing to the chip tester; and displaying the result.
Claim 15
Dependent Claim
62 words
The method of claim 12 further comprising the step, before the step of entering a number, of dividing the number indicative of a required speed of operation, and the step, after the step of starting the oscillator, of dividing the number of oscillator pulses by the same divisor as that used in dividing the number indicative of a required speed of operation.
Claim 16
Dependent Claim
8 words
The method of claim 13 wherein the divisor=2.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-24 | 1995-09-23 | 1996-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-24 | 1999-09-23 | 2000-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-24 | 2003-09-23 | 2004-03-24 | $7700.00 | Window Closed / Lapsed |