US5381087A
Expired / Lapsed
US
⏱️ 0.0 years remaining
LSI with built-in test circuit and testing method therefor
Assignee: Toshiba Corp
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Filing: 1992-04-28
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Granted: 1995-01-10
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Expires: 2012-04-28
Abstract
Abstract A high-speed LSI chip to be tested and evaluated by a readily available low-speed semiconductor tester and evaluation equipment. The high-speed LSI includes within the chip a clock supply circuit for supplying a high speed clock and an internal circuit, connected to the clock supply circuit, in which the high-speed clock is supplied from the clock supply circuit. A method for testing and evaluating the LSI chip. The method includes the steps of: supplying a high-speed clock generated from a clock supply circuit which is located within the semiconductor chip; and sending back a result of a semiconductor chip in response to the high-speed clock to the tester/evaluation equipment to be evaluated.
Inventors
- 👤 Masashi Hirano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 06:40
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318328
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
142 words
An integrated circuit having an internal circuit capable of being tested by a high-speed semiconductor chip tester to test and characterize the internal circuit comprising: a clock input terminal connected to the semiconductor chip tester; an on-chip clock supply circuit for supplying clock signals; a clock selection signal input terminal connected to the on-chip clock supply circuit; and the internal circuit connected to the clock supply circuit and receiving the clock signals, said clock selection signal input terminal supplying a test pattern to be applied to the internal circuit; wherein the clock supply circuit includes: a clock generation circuit for generating the clock signals; and a selection circuit for selecting an appropriate clock signal to be supplied to the internal circuit, the selection circuit being connected to the clock generation circuit, the clock input terminal, and the clock selection signal input terminal.
Claim 2
Dependent Claim
142 words
An integrated circuit having an internal circuit capable of being tested by a high-speed semiconductor chip tester to test and characterize the internal circuit comprising: a clock input terminal connected to the semiconductor chip tester; an on-chip clock supply circuit for supplying clock signals; a clock selection signal input terminal connected to the on-chip clock supply circuit; and the internal circuit connected to the clock supply circuit and receiving the clock signals, said clock selection signal input terminal supplying a test pattern to be applied to the internal circuit; wherein the clock supply circuit includes: a clock generation circuit for generating the clock signals; and a selection circuit for selecting an appropriate clock signal to be supplied to the internal circuit, the selection circuit being connected to the clock generation circuit, the clock input terminal, and the clock selection signal input terminal.
Claim 3
Dependent Claim
26 words
The integrated circuit according to claim 1, wherein the clock generation circuit includes means for generating high-speed clock signals having speeds of greater than 50 MHz.
Claim 4
Dependent Claim
34 words
The integrated circuit according to claim 1, further comprising a memory for receiving the clock signals from the clock supply circuit and outputting date to the internal circuit in response to the clock signals.
Claim 5
Dependent Claim
36 words
The integrated circuit according to claim 3, wherein the memory is a test pattern memory including means for outputting test patterns to the internal circuit synchronously with the clock signals supplied from the clock supply circuit.
Claim 6
Dependent Claim
35 words
The integrated circuit according to claim 3, wherein the memory is a cache memory including means for outputting a stored command to the internal circuit in response to an output of the clock supply circuit.
Claim 7
Dependent Claim
32 words
The integrated circuit according to claim 4, wherein the test pattern memory stores predetermined clock selection signals and automatically outputs, in a feedback manner, the clock selection signals from the selection circuit.
Claim 8
Dependent Claim
33 words
The integrated circuit according to claim 4, wherein the test pattern memory includes one of a read only memory (ROM), a programmable ROM, an erasable programmable ROM, and an electrically erasable programmable ROM.
Claim 9
Dependent Claim
32 words
The integrated circuit according to claim 1, wherein the clock generation circuit includes a phase-locked loop circuit, said generated clock signals from the phase-locked loop circuit being synchronous with the semiconductor tester.
Claim 10
Dependent Claim
34 words
The integrated circuit according to claim 8, further comprising a memory for receiving the clock signals from the clock supply circuit and outputting data to the internal circuit in response to the clock signals.
Claim 11
Dependent Claim
40 words
The integrated circuit according to claim 9, wherein the memory includes a test pattern memory including means for outputting test patterns to the internal circuit synchronously with the clock signals supplied from the phase-locked loop circuit through the selection circuit.
Claim 12
Dependent Claim
38 words
The integrated circuit according to claim 9, wherein the memory includes a cache memory including means for outputting stored commands to the internal circuit in response to an output of the phase-locked loop circuit through the selection circuit.
Claim 13
Dependent Claim
32 words
The integrated circuit according to claim 10, wherein the test pattern memory stores predetermined clock selection signals and automatically outputs, in a feedback manner, the clock selection signals from the selection circuit.
Claim 14
Dependent Claim
33 words
The integrated circuit according to claim 10, wherein the test pattern memory includes one of a read only memory (ROM), a programmable ROM, an erasable programmable ROM, and an electrically erasable programmable ROM.
References Cited (Backward Citations)
US4752729A
Cited
US4912709A
Cited
US4894605A
Cited
US5097205A
Cited
US5132614A
Cited
US5159263A
Cited
US5189365A
Cited
US5144230A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-09 | 1998-07-11 | 1999-01-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-09 | 2002-07-11 | 2003-01-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-09 | 2006-07-11 | 2007-01-10 | $7700.00 | Window Closed / Lapsed |