Computer memory architecture including a replacement cache

Claim 2

A microprocessor comprising: a semiconductor die; a microprocessor core situated on said semiconductor die; a first level set associative cache situated on said semiconductor die and coupled to said microprocessor core, said first level cache having a predetermined byte size, said first level cache storing a predetermined number of information entries; a replacement cache situated on said semiconductor die and coupled to said first level cache, said replacement cache storing information entries which are discarded from said first level cache as a result of first level cache misses, said replacement cache being at least as large as approximately one half the size of said first level cache; a clock controller supplying a clocking signal to the replacement cache when the replacement cache is accessed and terminating the clocking signal to the replacement cache when accessing of the replacement cache is finished so that power is conserved, a clocking signal being supplied to the microprocessor core and the first level set associative cache whether the clocking signal to the replacement cache is supplied or terminated.

Claim 3

The microprocessor of claim 1 further comprising a replacement cache hit detection circuit, coupled to said replacement cache, for detecting when a hit occurs in said replacement cache and for supplying a hit entry from said replacement cache to said first level cache when a hit occurs in said replacement cache.

Claim 4

The microprocessor of claim 1 further comprising memory accessing means for accessing an external memory to retrieve a desired information entry when both a first level cache miss and a replacement cache miss occur.

Claim 5

The microprocessor of claim 1 wherein said replacement cache comprises a set associative replacement cache.

Claim 6

The microprocessor of claim 1 wherein said replacement cache comprises a 4 way set associative replacement cache.

Claim 7

The microprocessor of claim 1 wherein said first level cache comprises a 4 way set associative cache.

Claim 8

A microprocessor according to claim 1 further comprising: a signal line coupled from the first level set associative cache to the clock controller for carrying a signal indicative of first level cache misses, the clock controller supplying the clocking signal for activating the replacement cache and terminating the clocking signal for deactivating the replacement cache based on the signal indicative of first level cache misses.

Claim 9

A microprocessor comprising: a semiconductor die; a microprocessor core situated on said semiconductor die; a first level set associative cache situated on said semiconductor die and coupled to said microprocessor core, said first level cache having a predetermined byte size, said first level cache storing a predetermined number of information entries; a first level cache hit detector, coupled to said first level cache, for detecting when a hit occurs in said first level cache and for discarding an entry from said first level cache as a discard information entry when a cache miss occurs in said first level cache; a replacement cache situated on said semiconductor die and coupled to said first level cache, said replacement cache storing discard information entries which are discarded from said first level cache as a result of first level cache misses, said replacement cache being at least as large as approximately one half the size of said first level cache; a replacement cache hit detector, coupled to said replacement cache, for detecting when a hit occurs in said replacement cache after a first level cache miss and for supplying a hit entry from said replacement cache to said first level cache when a hit occurs in said replacement cache; and a clock controller for providing a clocking signal to said replacement cache when said replacement cache is being accessed and for not providing said clocking signal to said replacement cache when said replacement cache is not being accessed, such that power is conserved, a clocking signal being supplied to the microprocessor core and the first level set associative cache whether the clocking signal to the replacement cache is provided or not provided.

Claim 10

A microprocessor comprising: a semiconductor die; a microprocessor core situated on said semiconductor die; a first level set associative cache situated on said semiconductor die and coupled to said microprocessor core, said first level cache having a predetermined byte size, said first level cache storing a predetermined number of information entries; a first level cache hit detector, coupled to said first level cache, for detecting when a hit occurs in said first level cache and for discarding an entry from said first level cache as a discard information entry when a cache miss occurs in said first level cache; a replacement cache situated on said semiconductor die and coupled to said first level cache, said replacement cache storing discard information entries which are discarded from said first level cache as a result of first level cache misses, said replacement cache being at least as large as approximately one half the size of said first level cache; a replacement cache hit detector, coupled to said replacement cache, for detecting when a hit occurs in said replacement cache after a first level cache miss and for supplying a hit entry from said replacement cache to said first level cache when a hit occurs in said replacement cache; and a clock controller for providing a clocking signal to said replacement cache when said replacement cache is being accessed and for not providing said clocking signal to said replacement cache when said replacement cache is not being accessed, such that power is conserved, a clocking signal being supplied to the microprocessor core and the first level set associative cache whether the clocking signal to the replacement cache is provided or not provided.

Claim 11

The microprocessor of claim 8 further comprising a first level cache hit detection circuit, situated in said first level cache, for detecting when a hit occurs in said first level cache and for discarding an entry from said first level cache as a discard information entry when a cache miss occurs in said first level cache.

Claim 12

The microprocessor of claim 8 further comprising an external memory for providing instructions and data to said microprocessor.

Claim 13

The microprocessor of claim 10 further comprising memory accessing means for accessing said external memory when both a first level cache miss occurs and a replacement cache miss occurs to retrieve a desired information entry from said external memory and send said desired information entry to said first level cache for storage therein.

Claim 14

The microprocessor of claim 8 wherein said replacement cache comprises a set associative replacement cache.

Claim 15

The microprocessor of claim 8 wherein said replacement cache comprises a 4 way set associative replacement cache.

Claim 16

The microprocessor of claim 8 wherein said first level cache comprises a 4 way set associative cache.

Claim 17

The microprocessor of claim 8 wherein said first level cache includes a first level instruction cache and a first level data cache.

Claim 18

A microprocessor according to claim 8 further comprising: a signal line coupled from the first level set associative cache to the clock controller for carrying a signal indicative of first level cache misses, the clock controller supplying the clocking signal for activating the replacement cache and terminating the clocking signal for deactivating the replacement cache based on the signal indicative of first level cache misses.

Claim 19

In a microprocessor including a microprocessor core situated on a semiconductor die, a main memory being situated external to said microprocessor and coupled to said microprocessor, a method of accessing memory comprising: storing information entries in a first level set associative cache which is coupled to the microprocessor core and which is situated on the semiconductor die; discarding an entry from said first level cache when a cache miss occurs in said first level cache, the entry thus discarded being designated the discard entry; storing said discard entry in a replacement cache for later use by said microprocessor core, said replacement cache being situated on the semiconductor die, said replacement cache being at least as large as approximately one half the size of said first level cache; said replacement cache supplying a hit entry to said first level cache when a cache hit occurs in said replacement cache, storing said hit entry in said first level cache for later use by said microprocessor core; clocking the replacement cache during time periods when the replacement cache is accessed; ceasing to clock the replacement cache during time periods when the replacement cache is not accessed; and clocking the microprocessor core and file first level cache during time periods when the replacement cache is accessed and not accessed.

Claim 20

In a microprocessor including a microprocessor core situated on a semiconductor die, a main memory being situated external to said microprocessor and coupled to said microprocessor, a method of accessing memory comprising: storing information entries in a first level set associative cache which is coupled to the microprocessor core and which is situated on the semiconductor die; discarding an entry from said first level cache when a cache miss occurs in said first level cache, the entry thus discarded being designated the discard entry; storing said discard entry in a replacement cache for later use by said microprocessor core, said replacement cache being situated on the semiconductor die, said replacement cache being at least as large as approximately one half the size of said first level cache; said replacement cache supplying a hit entry to said first level cache when a cache hit occurs in said replacement cache, storing said hit entry in said first level cache for later use by said microprocessor core; clocking the replacement cache during time periods when the replacement cache is accessed; ceasing to clock the replacement cache during time periods when the replacement cache is not accessed; and clocking the microprocessor core and file first level cache during time periods when the replacement cache is accessed and not accessed.

Claim 21

The method of claim 17 wherein said replacement cache is set associative.

Claim 22

The method of claim 17 wherein said first level cache is four-way set associative.

Claim 23

A method according to claim 17 further comprising the step of: clocking the replacement cache in response to a cache miss in the first level cache.

Claim 24

The method of claim 17 wherein said replacement cache is four-way set associative.