Patent US5619729A successfully refreshed from Google Patents.
US5619729A
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US
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Power management of DMA slaves with DMA traps
Assignee: Intel Corp
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Filing: 1996-01-11
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Granted: 1997-04-08
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Expires: 2016-01-11
Abstract
Abstract A device and method for power management of direct memory access ("DMA") slaves through DMA traps. The device comprises a plurality of registers coupled with conventional logic in order to generate a control signal for disabling direct memory access transfer requests for a powered-off DMA slave until the slave is re-powered. The method for managing power comprises steps of unmasking bits in a register containing information regarding which DMA slaves have been powered-off. Next, the DMA Controller consults a power management macro ("PMM") to determine whether a DMA transfer request involves a powered-off DMA slave. If not, the DMA transfer continues. However, if the DMA transfer does involve a powered-off DMA slave, then a main software application in operation is temporarily halted and the PMM generates a SMI signal and outputs the SMI signal to the central processing unit ("CPU") while keeping the disable control signal asserted, which effectively disables the DMA channel. The SMI signal invokes a software service routine which re-powers the powered-off DMA slave so that the main software application can continue.
Inventors
- 👤 Patrick M. Bland
- 👤 Richard G. Hofmann
- 👤 Robert T. Jackson
- 👤 Nader Amini
- 👤 Bechara F. Boury
- 👤 Jayesh Joshi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 21:28
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3206; G06F1/3215; G06F1/3225; G06F1/3234; G06F1/325; G06F1/3275; G06F13/00; G06F13/14; G06F13/20; G06F13/28; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 41
Claim 1
Independent Claim
113 words
An apparatus managing power usage of at least one device capable of performing direct memory accesses, the apparatus comprising: means for controlling a direct memory access by a selected direct memory access device of said at least one device; means for managing power status of said at least one device; and means for coupling said controlling means to said power managing means, said coupling means includes a plurality of handshaking signal lines including at least one direct memory access mask identification signal line transferring a signal from said controlling means into said power managing means to indicate that the direct memory access is to be performed by said selected direct memory access device.
Claim 2
Independent Claim
113 words
An apparatus managing power usage of at least one device capable of performing direct memory accesses, the apparatus comprising: means for controlling a direct memory access by a selected direct memory access device of said at least one device; means for managing power status of said at least one device; and means for coupling said controlling means to said power managing means, said coupling means includes a plurality of handshaking signal lines including at least one direct memory access mask identification signal line transferring a signal from said controlling means into said power managing means to indicate that the direct memory access is to be performed by said selected direct memory access device.
Claim 3
Dependent Claim
30 words
The apparatus according to claim 1, wherein a channel number, corresponding to said selected direct memory access device, is transferred from said means for controlling to said means for managing.
Claim 4
Dependent Claim
35 words
The apparatus according to claim 2, wherein the channel number corresponding to the selected direct memory access device propagates through the at least one direct memory access mask identification signal line in a binary representation.
Claim 5
Dependent Claim
49 words
The apparatus according to claim 1, wherein said plurality of handshaking signal lines further transfers an address strobe from said controlling means to said power managing means to indicate that the direct memory access has been requested between the selected direct memory access device and an external memory unit.
Claim 6
Dependent Claim
48 words
The apparatus according to claim 1, wherein said plurality of handshaking signal lines further includes at least one channel disable signal line, wherein the at least one channel disable signal line is activated if the power managing means determines that the selected direct memory access device is inoperative.
Claim 7
Dependent Claim
23 words
The apparatus according to claim 5, wherein the direct memory access is delayed if the at least one disable signal line is activated.
Claim 8
Dependent Claim
16 words
The apparatus according to claim 1, wherein said controlling means including a direct memory access controller.
Claim 9
Dependent Claim
27 words
The apparatus according to claim 7, wherein the power managing means includes a first storage element for storing power status information for said at least one device.
Claim 10
Dependent Claim
14 words
The apparatus according to claim 8, wherein said first storage element includes a register.
Claim 11
Dependent Claim
53 words
The apparatus according to claim 8, wherein the power managing means further includes a second storage element coupled to said first storage element via at least one control signal line, said second storage element is also coupled to said controlling means through said at least one direct memory access mask identification signal line.
Claim 12
Dependent Claim
17 words
The apparatus according to claim 10, wherein the second storage element includes at least one D-type register.
Claim 13
Independent Claim
122 words
An apparatus managing power usage of at least one device capable of performing direct memory accesses, said apparatus comprising: a direct memory access controller; and a power management device coupled to said direct memory access controller via a plurality of signal lines, said power management device prevents the direct memory access controller from supporting the direct memory access between the at least one device and an external memory unit, wherein said plurality of signal lines includes at least one mask identification signal line that transmits a channel number of a selected device of said at least one device chosen to perform the direct memory access, and at least one channel disable signal line that is activated when the selected device is inoperative.
Claim 14
Independent Claim
122 words
An apparatus managing power usage of at least one device capable of performing direct memory accesses, said apparatus comprising: a direct memory access controller; and a power management device coupled to said direct memory access controller via a plurality of signal lines, said power management device prevents the direct memory access controller from supporting the direct memory access between the at least one device and an external memory unit, wherein said plurality of signal lines includes at least one mask identification signal line that transmits a channel number of a selected device of said at least one device chosen to perform the direct memory access, and at least one channel disable signal line that is activated when the selected device is inoperative.
Claim 15
Dependent Claim
28 words
The apparatus according to claim 12, wherein the power management device includes a first storage element to store power status information pertaining to said at least one device.
Claim 16
Dependent Claim
43 words
The apparatus according to claim 13, wherein the power management device further includes a second storage element coupled to said first storage element via a plurality of control input signal lines and said direct memory access controller via said plurality of signal lines.
Claim 17
Dependent Claim
145 words
A computer system managing power usage of at least one device capable of performing direct memory accesses, said computer system comprising: bus means for transferring data; means for controlling an access to said bus means; means for processing data within said computer system, said processing means being coupled to said bus means; storing means for storing data; control means for controlling a direct memory access between said storing means and said at least one device, said control means generating a plurality of direct memory access control signals through at least one direct memory access control signal line; and power means for managing power status of said at least one device by generating a plurality of power management control signals to be inputted into said control means, said plurality of power management control signals including at least one signal for temporarily disabling the direct memory access.
Claim 18
Dependent Claim
145 words
A computer system managing power usage of at least one device capable of performing direct memory accesses, said computer system comprising: bus means for transferring data; means for controlling an access to said bus means; means for processing data within said computer system, said processing means being coupled to said bus means; storing means for storing data; control means for controlling a direct memory access between said storing means and said at least one device, said control means generating a plurality of direct memory access control signals through at least one direct memory access control signal line; and power means for managing power status of said at least one device by generating a plurality of power management control signals to be inputted into said control means, said plurality of power management control signals including at least one signal for temporarily disabling the direct memory access.
Claim 19
Dependent Claim
49 words
The computer system according to claim 15, wherein the plurality of direct memory access control signals include at least one direct memory access mask identification signal being a channel number identifying a selected direct memory access device of said at least one device chosen to perform direct memory access.
Claim 20
Dependent Claim
39 words
The computer system according to claim 16, wherein the at least one direct memory access mask identification signal is transmitted to the power means through a plurality of data bit lines as a binary representation of the channel number.
Claim 21
Dependent Claim
47 words
The computer system according to claim 17, wherein the plurality of direct memory access control signals includes an address strobe outputted from said control means, said address strobe indicating that direct memory access has been requested between the selected direct memory access device and said storing means.
Claim 22
Dependent Claim
62 words
The computer system according to claim 18, wherein the at least one signal for temporarily disabling direct memory access is transmitted from the power means and into the control means through at least one channel disable signal line, the at least one channel disable signal line is activated if the power means determines that the selected direct memory access device is inoperative.
Claim 23
Dependent Claim
43 words
The computer system according to claim 19, wherein said power means further generates at least one system management interrupt signal to request a software service routine to power-on the selected direct memory access device if the selected direct memory access device is powered-off.
Claim 24
Dependent Claim
273 words
A computer system for managing power usage by a plurality of direct memory access devices each capable of performing a direct memory access, said computer system comprising: a system bus; at least one central processing unit coupled to said system bus; at least one bus controller coupled to said system bus; at least one memory unit coupled to said system bus; a direct memory access controller coupled to said system bus and said memory unit, said direct memory access controller generates a first plurality of control signals through a plurality of direct memory access control signal lines, said first plurality of control signals includes at least one direct memory access mask identification signal transmitting a channel number identifying a selected direct memory access device of the plurality of direct memory access devices selected to perform the direct memory access, and an address strobe outputted from said direct memory access controller, said address strobe indicating that direct memory access has been requested between the selected direct memory access device and said at least one memory unit; and a power management device coupled to said system bus and said direct memory access controller, said power management device manages power status of the plurality of direct memory access devices by generating a second plurality of control signals to be inputted into said direct memory access controller, said second plurality of control signals being at least one control signal to temporarily disable the direct memory access, and at least one system management interrupt signal to request a software service routine to power-on the selected direct memory access device if said selected direct memory access device is powered-off.
Claim 25
Dependent Claim
273 words
A computer system for managing power usage by a plurality of direct memory access devices each capable of performing a direct memory access, said computer system comprising: a system bus; at least one central processing unit coupled to said system bus; at least one bus controller coupled to said system bus; at least one memory unit coupled to said system bus; a direct memory access controller coupled to said system bus and said memory unit, said direct memory access controller generates a first plurality of control signals through a plurality of direct memory access control signal lines, said first plurality of control signals includes at least one direct memory access mask identification signal transmitting a channel number identifying a selected direct memory access device of the plurality of direct memory access devices selected to perform the direct memory access, and an address strobe outputted from said direct memory access controller, said address strobe indicating that direct memory access has been requested between the selected direct memory access device and said at least one memory unit; and a power management device coupled to said system bus and said direct memory access controller, said power management device manages power status of the plurality of direct memory access devices by generating a second plurality of control signals to be inputted into said direct memory access controller, said second plurality of control signals being at least one control signal to temporarily disable the direct memory access, and at least one system management interrupt signal to request a software service routine to power-on the selected direct memory access device if said selected direct memory access device is powered-off.
Claim 26
Dependent Claim
26 words
The computer system according to claim 21, wherein the second plurality of control signals further include at least one direct memory access mask identification signal line.
Claim 27
Independent Claim
124 words
A method for managing power usage by at least one device capable of performing direct memory access, said method comprising the steps of: receiving a signal indicating that a DMA is requested for a selected direct memory access slave device; receiving a channel number corresponding to the selected direct memory access slave device; determining whether the selected direct memory access slave device is operational; asserting a disable signal line corresponding to said channel number of the selected direct memory access device if the selected direct memory access slave device is not operative; requesting a system management interrupt to invoke a software service routine to re-power the selected direct memory access slave device; and deasserting the disable line upon completion of the software service routine.
Claim 28
Independent Claim
124 words
A method for managing power usage by at least one device capable of performing direct memory access, said method comprising the steps of: receiving a signal indicating that a DMA is requested for a selected direct memory access slave device; receiving a channel number corresponding to the selected direct memory access slave device; determining whether the selected direct memory access slave device is operational; asserting a disable signal line corresponding to said channel number of the selected direct memory access device if the selected direct memory access slave device is not operative; requesting a system management interrupt to invoke a software service routine to re-power the selected direct memory access slave device; and deasserting the disable line upon completion of the software service routine.
Claim 29
Independent Claim
65 words
An apparatus to manage power usage of a direct memory access device, the apparatus comprising: a direct memory access controller; and a power management device coupled to the direct memory access controller, said power management device signals said direct memory access controller to prevent a direct memory access from being requested of the direct memory access device when the direct memory access device is inoperative.
Claim 30
Independent Claim
65 words
An apparatus to manage power usage of a direct memory access device, the apparatus comprising: a direct memory access controller; and a power management device coupled to the direct memory access controller, said power management device signals said direct memory access controller to prevent a direct memory access from being requested of the direct memory access device when the direct memory access device is inoperative.
Claim 31
Dependent Claim
34 words
The apparatus according to claim 24, wherein said power management device is coupled to said direct memory access controller through an address strobe line to signal that said direct memory access has been requested.
Claim 32
Dependent Claim
44 words
The apparatus according to claim 25, wherein said power management device is also coupled to said direct memory access controller through at least one direct memory access mask identification line to indicate that the device has been selected to perform the direct memory access.
Claim 33
Dependent Claim
37 words
The apparatus according to claim 26, wherein said power management device is coupled to said direct memory access controller through at least one channel disable line to disable the direct memory access until the device is operative.
Claim 34
Dependent Claim
32 words
The apparatus according to claim 24, wherein said power management device is coupled to said direct memory access controller through at least one channel disable line to disable the direct memory access.
Claim 35
Dependent Claim
91 words
A computer system managing power usage of a direct memory access device, the computer system comprising: a bus; a processor coupled to said bus; a memory unit coupled to said bus; a direct memory access controller coupled to said bus and said memory unit; and a power management device coupled to at least the direct memory access controller said power management device signals said direct memory access controller to prevent a direct memory access from being requested of the direct memory access device when the direct memory access device is inoperative.
Claim 36
Dependent Claim
91 words
A computer system managing power usage of a direct memory access device, the computer system comprising: a bus; a processor coupled to said bus; a memory unit coupled to said bus; a direct memory access controller coupled to said bus and said memory unit; and a power management device coupled to at least the direct memory access controller said power management device signals said direct memory access controller to prevent a direct memory access from being requested of the direct memory access device when the direct memory access device is inoperative.
Claim 37
Dependent Claim
26 words
The computer system according to claim 29, wherein the power management device is coupled to the direct memory access controller via a plurality of signal lines.
Claim 38
Dependent Claim
52 words
The computer system according to claim 30, wherein said plurality of signal lines included an address strobe line to transmit an address strobe signal from the direct memory access controller to said power management device to indicate that the direct memory access has been requested between the device and said memory unit.
Claim 39
Dependent Claim
54 words
The computer system according to claim 31, wherein said plurality of signal lines further includes at least one direct memory access mask identification line to transmit a mask signal from said direct memory access controller to said power management device to indicate that the device has been selected to perform the direct memory access.
Claim 40
Dependent Claim
33 words
The computer system according to claim 31 includes at least one channel disable signal line to cause said direct memory access controller to disable the direct memory access if the device is inoperative.
Claim 41
Dependent Claim
30 words
The computer system according to claim 33, where said at least one channel disable signal line is used to temporarily disable the direct memory access until the device is operative.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-07 | 2000-10-07 | 2001-04-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-07 | 2004-10-07 | 2005-04-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-07 | 2008-10-07 | 2009-04-08 | $7700.00 | Window Closed / Lapsed |