US5619147A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS buffer with controlled slew rate
Assignee: Texas Instruments Inc
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Filing: 1995-06-05
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Granted: 1997-04-08
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Expires: 2015-06-05
Abstract
Abstract A method and apparatus for a circuit physically realizing a CMOS buffer with a controlled slew rate at the output and using no additional standby power to achieve the slew rate control is described. A feedback path from the output is coupled to transistors comprising a differential pair, the transistors are further coupled to a capacitance. The discharge rate of the capacitance and the size choices of the transistors in the circuit are used with the feedback path to control the high-to-low and low-to high transition rate of the output. The circuit of the invention allows a system designer to construct a buffer for driving a bus with excellent on chip and bus signal noise characteristics using standard digital CMOS technology and having excellent standby and active power characteristics. An open drain buffer and a push-pull buffer are described. An integrated circuit implementing application logic coupled to input/output and output buffers embodying this circuit is disclosed. Other embodiments are also disclosed.
Inventors
- 👤 Steven A. Hunley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:26
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/16; H03K17/161; H03K17/165; H03K17/166; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
158 words
A method of controlling slew rate on an output terminal, comprising the steps of: activating an output transistor; comparing a voltage on the output terminal to an internal node voltage during output transistor activation; and decreasing the rate of a voltage transition at the output terminal in response to the comparison of the output terminal to the internal node voltage; wherein comparing the output voltage to the internal node voltage during out put transistor activation comprises the steps of: establishing the internal node voltage and its rate of transition; monitoring the voltage transition at the output terminal; and detecting, a condition of excessive output terminal voltage transition speed by comparing the relative position in time of the output terminal voltage transition to the internal node voltage transition; and wherein establishing the internal node voltage and its rate of transition comprises charging a capacitor to a predetermined voltage level and causing the capacitor to discharge through a resistive path.
Claim 2
Independent Claim
158 words
A method of controlling slew rate on an output terminal, comprising the steps of: activating an output transistor; comparing a voltage on the output terminal to an internal node voltage during output transistor activation; and decreasing the rate of a voltage transition at the output terminal in response to the comparison of the output terminal to the internal node voltage; wherein comparing the output voltage to the internal node voltage during out put transistor activation comprises the steps of: establishing the internal node voltage and its rate of transition; monitoring the voltage transition at the output terminal; and detecting, a condition of excessive output terminal voltage transition speed by comparing the relative position in time of the output terminal voltage transition to the internal node voltage transition; and wherein establishing the internal node voltage and its rate of transition comprises charging a capacitor to a predetermined voltage level and causing the capacitor to discharge through a resistive path.
Claim 3
Dependent Claim
41 words
The method of claim 1 wherein activating an output transistor comprises the step of switching an input terminal from a first voltage value to a second voltage value wherein the output transistor initiates activation in response to the input terminal switching.
Claim 4
Dependent Claim
33 words
The method of claim 1 wherein monitoring the voltage transition at the output terminal comprises comparing the voltage at the output terminal as it changes to the internal node voltage as it changes.
Claim 5
Independent Claim
172 words
A method of controlling slew rate on an output terminal, comprising the steps of: activating an output transistor; comparing a voltage on the output terminal to an internal node voltage during output transistor activation; and decreasing the rate of a voltage transition at the output terminal in response to the comparison of the output terminal to the internal node voltage: wherein comparing the output voltage to the internal node voltage output transistor activation comprises the steps of: establishing the internal node voltage and its rate of transition; monitoring the voltage transition at the output terminal; and detecting a condition of excessive output terminal voltage transition speed by comparing the relative position in time of the output terminal voltage transition to the internal node voltage transition; and wherein the compared relative position in time of the output terminal voltage transition to the internal node voltage transition is directly related to a capacitive load condition which will cause a predetermined output terminal voltage transition speed in the absence of any output transistor activation modulation.
Claim 6
Independent Claim
172 words
A method of controlling slew rate on an output terminal, comprising the steps of: activating an output transistor; comparing a voltage on the output terminal to an internal node voltage during output transistor activation; and decreasing the rate of a voltage transition at the output terminal in response to the comparison of the output terminal to the internal node voltage: wherein comparing the output voltage to the internal node voltage output transistor activation comprises the steps of: establishing the internal node voltage and its rate of transition; monitoring the voltage transition at the output terminal; and detecting a condition of excessive output terminal voltage transition speed by comparing the relative position in time of the output terminal voltage transition to the internal node voltage transition; and wherein the compared relative position in time of the output terminal voltage transition to the internal node voltage transition is directly related to a capacitive load condition which will cause a predetermined output terminal voltage transition speed in the absence of any output transistor activation modulation.
Claim 7
Independent Claim
119 words
A method of controlling slew rate on an output terminal comprising the steps of: activating an output transistor; comparing a voltage on the output terminal to an internal node voltage during output transistor activation; and decreasing the rate of a voltage transition at the output terminal in response to the comparison of the output terminal to the internal node voltage; wherein decreasing the rate of voltage transition at the output terminal comprises the steps of: activating an internal component, whereby the activation of the internal component draws a first current; and decreasing a second current by the first current amount, whereby the second current reduction affects the output transistor control thus decreasing the transition rate at the output terminal.
Claim 8
Independent Claim
119 words
A method of controlling slew rate on an output terminal comprising the steps of: activating an output transistor; comparing a voltage on the output terminal to an internal node voltage during output transistor activation; and decreasing the rate of a voltage transition at the output terminal in response to the comparison of the output terminal to the internal node voltage; wherein decreasing the rate of voltage transition at the output terminal comprises the steps of: activating an internal component, whereby the activation of the internal component draws a first current; and decreasing a second current by the first current amount, whereby the second current reduction affects the output transistor control thus decreasing the transition rate at the output terminal.
Claim 9
Dependent Claim
71 words
The method of claim 5 wherein comparing the output voltage to the internal node voltage during output transistor activation comprises the steps of: establishing the internal mode voltage and its rate of transition; monitoring the voltage transition at the output terminal; and detecting a condition of excessive output terminal voltage transition speed by comparing the relative position in time of the output terminal voltage transition to the internal node voltage transition.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-07 | 2000-10-07 | 2001-04-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-07 | 2004-10-07 | 2005-04-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-07 | 2008-10-07 | 2009-04-08 | $7700.00 | Window Closed / Lapsed |