US5619033A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Layered solid state photodiode sensor array
Assignee: Xerox Corp
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Filing: 1995-06-07
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Granted: 1997-04-08
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Expires: 2015-06-07
Abstract
Abstract A photodetecting device and a method for constructing the photodetecting device. The photodetecting device provides at least one transistor formed over a substrate and at least one photodiode formed over the at least one transistor. Each of the at least one photodiode is coupled to one of the at least one transistor. The fill factor of the photodiode is very high even when the resolution of the photodetecting device is increased. The photodetecting devices are formed in a matrix having rows and columns. The matrix of photodetecting devices forms a two dimensional imaging device.
Inventors
- 👤 Richard L. Weisfield
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 05:57
CPC Classifications
H; H10; H10F; H10F39/00; H10F39/10; H10F39/12; H10F39/18
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
61 words
A photodetecting device, comprising: a substrate; at least one transistor formed over the substrate; and at least one photodiode formed over the at least one transistor, wherein each of the at least one photodiode is coupled to one of the at least one transistor, and the coupling comprises an electrical connection between the photodiode and a drain electrode of the transistor.
Claim 2
Dependent Claim
61 words
A photodetecting device, comprising: a substrate; at least one transistor formed over the substrate; and at least one photodiode formed over the at least one transistor, wherein each of the at least one photodiode is coupled to one of the at least one transistor, and the coupling comprises an electrical connection between the photodiode and a drain electrode of the transistor.
Claim 3
Dependent Claim
68 words
The device of claim 1, wherein a first passivation layer is formed between the at least one transistor and the at least one photodiode, each of the at least one photodiode comprising: an n+ layer formed over the first passivation layer; an amorphous silicon layer formed over the n+ layer; a p+ layer formed over the amorphous silicon layer; and a conductive layer formed over the p+ layer.
Claim 4
Dependent Claim
52 words
The device of claim 2, wherein: the n+ layer is about 500 angstroms to about 1000 angstroms thick; the amorphous silicon layer is about 0.5 microns to about 2.0 microns thick; the p+ layer is about 100 angstroms thick; and the conductive layer is about 500 angstroms to about 1000 angstroms thick.
Claim 5
Dependent Claim
36 words
The device of claim 2, each of the at least one photodiode further comprising a bias contact formed over the conductive layer, wherein the bias contact shields one of the at least one transistor from light.
Claim 6
Dependent Claim
41 words
The device of claim 2, wherein the at least one photodiode is arranged in a matrix having at least one row and at least one column, each of the at least one photodiode being separated from adjacent photodiodes by a notch.
Claim 7
Dependent Claim
17 words
The device of claim 5, wherein the notch is about 3 microns to about 10 microns wide.
Claim 8
Dependent Claim
14 words
The device of claim 5, wherein the notch is formed in the n+ layer.
Claim 9
Dependent Claim
32 words
The device of claim 5, wherein a metal layer is formed between the n+ layer and the first passivation layer, the notch being formed in the metal layer and the n+ layer.
Claim 10
Dependent Claim
25 words
The device of claim 5, wherein the notch is formed in the conductive layer, the p+ layer, the amorphous silicon layer and the n+ layer.
Claim 11
Dependent Claim
42 words
The device of claim 5, wherein a metal layer is formed between the n+ layer and the first passivation layer, the notch being formed in the conductive layer, the p+ layer, the amorphous silicon layer, the n+ layer, and the metal layer.
Claim 12
Dependent Claim
66 words
The device of claim 2, further comprising: at least one via hole formed in the first passivation layer, each of the at least one via hole exposing a drain electrode of one of the at least one transistor, the n+ layer contacting the drain electrode of the at least one transistor through each of the at least one via hole forming at least one back contact.
Claim 13
Dependent Claim
19 words
The device of claim 11, wherein each of the at least one back contact is about 10 microns wide.
Claim 14
Dependent Claim
80 words
The device of claim 2, further comprising: at least one via hole formed in the first passivation layer, each of the at least one via hole exposing a drain electrode of one of the at least one transistor; and a metal layer formed between the n+ layer and the first passivation layer, the metal layer contacting the drain electrode of the at least one transistor through each of the at least one via hole forming at least one back contact.
Claim 15
Dependent Claim
17 words
The device of claim 13, wherein the at least one back contact is about 10 microns wide.
Claim 16
Independent Claim
61 words
A method for manufacturing a photodetecting device, comprising: forming at least one transistor over a substrate; and forming at least one photodiode over the at least one transistor, each of the at least one photodiode being coupled to one of the at least one transistor, the coupling comprising an electrical connection between the photodiode and a drain electrode of the transistor.
Claim 17
Independent Claim
61 words
A method for manufacturing a photodetecting device, comprising: forming at least one transistor over a substrate; and forming at least one photodiode over the at least one transistor, each of the at least one photodiode being coupled to one of the at least one transistor, the coupling comprising an electrical connection between the photodiode and a drain electrode of the transistor.
Claim 18
Dependent Claim
57 words
The method of claim 15, further comprising: forming a first passivation layer over the at least one transistor formed over the substrate; forming an n+ layer over the passivation layer; forming an amorphous silicon layer over the n+ layer; forming a p+ layer over the amorphous silicon layer; and forming a conductive layer over the p+ layer.
Claim 19
Dependent Claim
41 words
The method of claim 16, wherein the at least one photodiode is arranged in a matrix having at least one row and at least one column, each of the at least one photodiode being separated from adjacent photodiodes by a notch.
Claim 20
Dependent Claim
20 words
The method of claim 17, wherein the notch is formed by; masking the n+ layer; and etching the n+ layer.
Claim 21
Dependent Claim
40 words
The method of claim 17, further comprising forming a metal layer between the n+ layer and the first passivation layer, wherein the notch is formed by; masking the n+ layer; and etching through the n+ layer and the metal layer.
Claim 22
Dependent Claim
74 words
The method of claim 16, further comprising: masking the first passivation layer; etching the first passivation layer to form at least one via hole exposing a drain electrode of each of the at least one transistor; and forming the n+ layer over the first passivation layer, the n+ layer contacting the drain electrode of each of the at least one transistor through the at least one via hole forming at least one back contact.
Claim 23
Dependent Claim
79 words
The method of claim 16, further comprising: masking the first passivation layer; etching the first passivation layer to form at least one via hole exposing a drain electrode of each one of the at least one transistor; and forming a metal layer between the first passivation layer and the n+ layer, the metal layer contacting the drain electrode of each of the at least one transistor through the at least one via hole forming at least one back contact.
References Cited (Backward Citations)
US4670765A
Cited
EP0163956A2
Cited
US4672454A
Cited
US4675739A
Cited
US4785186A
Cited
US5164809A
Cited
US5079426A
Cited
US5017989A
Cited
US5117114A
Cited
US5420452A
Cited
US5235195A
Cited
US5396072A
Cited
US5319206A
Cited
US5516712A
Cited
US5381014A
Cited
US5381014B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-07 | 2000-10-07 | 2001-04-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-07 | 2004-10-07 | 2005-04-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-07 | 2008-10-07 | 2009-04-08 | $7700.00 | Window Closed / Lapsed |