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US5319206A Expired / Lapsed US ⏱️ 0.0 years remaining

Method and apparatus for acquiring an X-ray image using a solid state device

Assignee: Sterling Diagnostic Imaging Inc
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Filing: 1992-12-16
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Granted: 1994-06-07
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Expires: 2012-12-16
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Abstract

Abstract An X-ray image capture element includes a dielectric substrate layer having a top surface and a bottom surface. A plurality of transistors is arrayed adjacent the top surface of the dielectric layer. A plurality of charge storage capacitors is also arrayed adjacent the top surface of the dielectric layer, each capacitor having a conductive inner microplate connected to at least one of the transistors. Conductive address lines and sense lines are disposed adjacent the top surface of the dielectric layer for electronically activating the transistors and individually accessing each of the capacitors. A photoconductive layer is disposed over the transistors, address and sense lines, and a top conducting layer is disposed over the photoconductive layer opposite the dielectric layer. The image capture element also includes a plurality of charge barrier layers disposed adjacent, respectively, the top surface of each of the inner microplates, and a barrier dielectric layer disposed between and coextensive with the photoconductive layer and the top conducting layer.

Inventors

  • 👤 Denny L. Y. Lee
  • 👤 Lawrence K. Cheung

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 09:52
CPC Classifications
G; G01; G01T; G01T1/00; G01T1/29; G01T1/2914; G01T1/2921; G01T1/2928; H; H10; H10F; H10F39/00; H10F39/10; H10F39/12; H10F39/191; H10F39/195

Claims Analysis

Total Claims: 16
Claim 1
Independent Claim 162 words
In an image capture element including a dielectric substrate layer having a top surface and a bottom surface, a plurality of transistors arrayed adjacent the top surface of said dielectric layer, a plurality of charge storage capacitors also arrayed adjacent the top surface of said dielectric layer, each capacitor having a conductive inner microplate connected to at least one of said transistors, said inner microplate having a top surface opposite said dielectric layer, means disposed adjacent the top surface of said dielectric layer for electronically activating said transistors and individually accessing each of said capacitors, a photoconductive layer disposed over said transistors and said means for activating and accessing, and a top conducting layer disposed over said photoconductive layer opposite said dielectric layer, the improvement comprising a plurality of charge barrier layers disposed adjacent, respectively, the top surface of each of said inner microplates, and a barrier dielectric layer disposed between and coextensive with said photoconductive layer and said top conducting layer.
Claim 2
Dependent Claim 162 words
In an image capture element including a dielectric substrate layer having a top surface and a bottom surface, a plurality of transistors arrayed adjacent the top surface of said dielectric layer, a plurality of charge storage capacitors also arrayed adjacent the top surface of said dielectric layer, each capacitor having a conductive inner microplate connected to at least one of said transistors, said inner microplate having a top surface opposite said dielectric layer, means disposed adjacent the top surface of said dielectric layer for electronically activating said transistors and individually accessing each of said capacitors, a photoconductive layer disposed over said transistors and said means for activating and accessing, and a top conducting layer disposed over said photoconductive layer opposite said dielectric layer, the improvement comprising a plurality of charge barrier layers disposed adjacent, respectively, the top surface of each of said inner microplates, and a barrier dielectric layer disposed between and coextensive with said photoconductive layer and said top conducting layer.
Claim 3
Dependent Claim 46 words
The element in accordance with claim 1, wherein each capacitor also comprises a conductive outer microplate disposed on the top surface of said dielectric layer, and dielectric material disposed over said outer microplate, said inner microplate being disposed over said dielectric material opposite said outer microplate.
Claim 4
Dependent Claim 22 words
The element in accordance with claim 2, wherein said inner microplates comprise aluminum and wherein said charge barrier layers comprise aluminum oxide.
Claim 5
Dependent Claim 14 words
The element in accordance with claim 2, wherein said inner microplates comprise indium-tin oxide.
Claim 6
Dependent Claim 40 words
The element in accordance with claim 2, wherein each transistor is a thin-film field effect transistor (FET) having a source connected to one of said inner microplates, and a drain and a gate both connected to said means for activating.
Claim 7
Dependent Claim 28 words
The element in accordance with claim 5, wherein said transistor comprises a material selected from the group consisting of amorphous silicon, polycrystalline silicon, crystalline silicon and cadmium selenide.
Claim 8
Dependent Claim 22 words
The element in accordance with claim 5, further comprising a passivation layer disposed between said photoconductive layer and each of said transistors.
Claim 9
Dependent Claim 66 words
The element in accordance with claim 5, wherein the means for activating and accessing comprise: a plurality of discrete conductive address lines extending along the transistors and being connected, respectively, to the gates of adjacent transistors, and a plurality of discrete conductive sense lines extending along the transistors in a direction across the address lines and being connected, respectively, to the drain regions of adjacent transistors.
Claim 10
Dependent Claim 31 words
The element in accordance with claim 8, further comprising means for applying a variable operating voltage to the top conducting layer relative to a ground voltage maintained at the outer microplates.
Claim 11
Dependent Claim 29 words
The element in accordance with claim 8, further comprising means for switching said address lines and said sense lines from a first charge state to a second readout state.
Claim 12
Dependent Claim 28 words
The element in accordance with claim 8, further comprising charge measuring means connected to said sense lines for converting electrical charge stored in said capacitors into analog signals.
Claim 13
Dependent Claim 46 words
The element in accordance with claim 1, in combination with an enclosure surrounding said element to form a portable electronic cassette, said enclosure including an external electrical cable connected to said element for providing power to said element and for reading electrical signals from said element.
Claim 14
Independent Claim 468 words
A method for capturing a radiogram on an image capture element comprising: a dielectric substrate layer having a top surface and a bottom surface; a plurality of transistors arrayed adjacent the top surface of said dielectric layer; a plurality of charge storage capacitors also arrayed adjacent the top surface of said dielectric layer, each capacitor having a conductive inner microplate connected to at least one of said transistors, each inner microplate having a top surface opposite said dielectric layer, each capacitor also having a conductive outer microplate disposed on the top surface of said dielectric layer, dielectric material disposed over said outer microplate, said inner microplate being disposed over said dielectric material opposite said outer microplate; means disposed adjacent the top surface of said dielectric layer for electronically activating said transistors and individually accessing each of said capacitors, said means for activating and accessing including a plurality of discrete conductive address lines extending along the transistors and being connected, respectively, to gates of adjacent transistors, and a plurality of discrete conductive sense lines extending along the transistors in a direction across the address lines and being connected, respectively, to drain regions of adjacent transistors; charge amplifying means connected, respectively, to said sense lines for converting electrical charge in said capacitors into analog signals; a photoconductive layer disposed over said transistors and said means for activating and accessing; a top conducting layer disposed over said photoconductive layer opposite said dielectric layer; a plurality of charge barrier layers disposed adjacent, respectively, the top surface of each of said inner microplates; and a barrier dielectric layer disposed between and coextensive with said photoconductive layer and said top conducting layer, the method comprising: (a) bringing all address lines to a first bias value, connecting said inner microplates to electrical ground potential, and setting said charge storage capacitors to a no-signal level; (b) applying a positive operating voltage to the top conducting layer while maintaining said outer microplates at electrical ground potential; (c) removing said first bias value from all address lines so that said charge storage capacitors are capable of accumulating electrical charges; (d) exposing the photoconductive layer to imagewise modulated radiation, causing electrical charges to be generated within the photoconductive layer at a density proportional to the amount of radiation; (e) stopping the radiation and disconnecting the initial positive operating voltage applied to the top conducting layer, effectively creating a distribution of electrical charges within the image capture element; (f) applying a signal sequentially through the plurality of address lines to the transistors, so as to allow the charges collected in the capacitors to flow from the capacitors into the plurality of sense lines; and (g) activating the charge amplifying means to accumulate the charges from each charge storage capacitor, this cumulative value later being digitized and stored in memory 1.
Claim 15
Independent Claim 468 words
A method for capturing a radiogram on an image capture element comprising: a dielectric substrate layer having a top surface and a bottom surface; a plurality of transistors arrayed adjacent the top surface of said dielectric layer; a plurality of charge storage capacitors also arrayed adjacent the top surface of said dielectric layer, each capacitor having a conductive inner microplate connected to at least one of said transistors, each inner microplate having a top surface opposite said dielectric layer, each capacitor also having a conductive outer microplate disposed on the top surface of said dielectric layer, dielectric material disposed over said outer microplate, said inner microplate being disposed over said dielectric material opposite said outer microplate; means disposed adjacent the top surface of said dielectric layer for electronically activating said transistors and individually accessing each of said capacitors, said means for activating and accessing including a plurality of discrete conductive address lines extending along the transistors and being connected, respectively, to gates of adjacent transistors, and a plurality of discrete conductive sense lines extending along the transistors in a direction across the address lines and being connected, respectively, to drain regions of adjacent transistors; charge amplifying means connected, respectively, to said sense lines for converting electrical charge in said capacitors into analog signals; a photoconductive layer disposed over said transistors and said means for activating and accessing; a top conducting layer disposed over said photoconductive layer opposite said dielectric layer; a plurality of charge barrier layers disposed adjacent, respectively, the top surface of each of said inner microplates; and a barrier dielectric layer disposed between and coextensive with said photoconductive layer and said top conducting layer, the method comprising: (a) bringing all address lines to a first bias value, connecting said inner microplates to electrical ground potential, and setting said charge storage capacitors to a no-signal level; (b) applying a positive operating voltage to the top conducting layer while maintaining said outer microplates at electrical ground potential; (c) removing said first bias value from all address lines so that said charge storage capacitors are capable of accumulating electrical charges; (d) exposing the photoconductive layer to imagewise modulated radiation, causing electrical charges to be generated within the photoconductive layer at a density proportional to the amount of radiation; (e) stopping the radiation and disconnecting the initial positive operating voltage applied to the top conducting layer, effectively creating a distribution of electrical charges within the image capture element; (f) applying a signal sequentially through the plurality of address lines to the transistors, so as to allow the charges collected in the capacitors to flow from the capacitors into the plurality of sense lines; and (g) activating the charge amplifying means to accumulate the charges from each charge storage capacitor, this cumulative value later being digitized and stored in memory 1.
Claim 16
Dependent Claim 141 words
A method according to claim 13, further restoring the image capture element to its original state, comprising: (a) applying a gate signal through the address lines to the transistors so as to allow all charges remaining in the charge storage capacitors to flow from the capacitors into the sense lines; (b) electrically grounding the charge amplifying means connected to ensure an electrically neutral ground at each charge storage capacitor; (c) reconnecting the positive operating voltage to the top conducting layer and, at a controlled rate, decreasing the voltage to an electrically neutral ground value and then with reversed polarity continuing to decrease the voltage to a second operating negative voltage so as to neutralize any electrical charges remaining in the photoconductive layer; and (d) reducing the reversed operating voltage back to electrically neutral ground voltage, effectively re-initializing the image capture element.

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-06-06 1997-12-06 1998-06-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-06-06 2001-12-06 2002-06-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-06-06 2005-12-06 2006-06-07 $7700.00 Window Closed / Lapsed

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