Method of making CMOS output buffer with enhanced ESD resistance

Claim 1

In a method of fabricating an integrated circuit structure, the steps of: a) forming a structure having a silicon substrate and a field oxide thereon, said field oxide leaving exposed a core NMOS region, a core PMOS region, an output NMOS region, and an output PMOS region, said NMOS regions being p-type and said PMOS regions being n-type; b) after step a, forming a gate oxide layer; c) after step b, depositing and patterning a polysilicon layer so as to define a core NMOS gate, a core PMOS gate, an output NMOS gate, and an output PMOS gate, said patterning being performed so that the channel lengths of said output gates are greater than the channel lengths of said core gates; d1) after step c, performing a relatively light and deep p-type implant into said core NMOS region while masking said output NMOS region and said PMOS regions; d2) after step c, performing a relatively light and deep n-type implant into said core PMOS region while masking said output PMOS region and said NMOS regions; e) after steps d, forming sidewalls on said gates; and f1) after step e, masking said NMOS regions while leaving exposed said PMOS regions, and peribrining a relatively deep and heavy p-type implant to define a core PMOS drain, a core PMOS source, an output PMOS drain, and an output PMOS source; and f2) after step e, masking said PMOS regions while leaving exposed said NMOS regions, and performing a relatively deep and heavy n-type implant to define a core NMOS drain, a core NMOS source, an output NMOS drain, and an output NMOS source.