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Patent US5616510A successfully refreshed from Google Patents.
US5616510A
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Method for making multimedia storage system with highly compact memory cells
Assignee: Individual
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Filing: 1995-06-06
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Granted: 1997-04-01
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Expires: 2015-06-06
Abstract
Abstract A highly compact nonvolatile solid state memory core is provided that stores and reproduces both digital and analog signals for multimedia applications. The memory core includes vertical electrically erasable and programmable read only memories (EEPROM) cells having, for example, a stacked gate or a split channel configuration. An array of EEPROM cells on the same chip is prewritten and is used as a reference for digital-analog conversions and for memory cell programming. An intelligent write method allows each memory cell to either store an analog signal or multiple digital signals. Based on the previously stored signal, the intelligent write method determines whether to charge or to discharge the floating gate associated with the selected memory cell. Thus, full erasure is not required prior to programming each memory cell. The present invention significantly increases the density of memory cell arrays while prolonging the useful life of the array.
Inventors
- 👤 Chun C. D. Wong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:58
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C11/5635; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; G11C16/06; G11C16/34; G11C16/3436; G11C16/3468; G11C16/3472; G11C16/3481; G11C27/00; G11C27/005; H; H10; H10B; H10B41/00; H10B41/20; H10B41/23; H10B41/27; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; G11C2211/00; G11C2211/56; G11C2211/562; G11C2211/5621; G11C2211/5624; G11C2211/563; G11C2211/5634
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
83 words
A method of forming a vertical memory cell comprising the steps of: doping a substrate to form a source region; forming a channel region on said source region; forming a drain region on said channel region, wherein said drain region includes an extended drain region to provide a tunneling electrical field enhancement effect; forming a trench through said drain region and said channel region; forming a floating gate in said trench; and forming a control gate in operative relation to said floating gate.
Claim 2
Independent Claim
83 words
A method of forming a vertical memory cell comprising the steps of: doping a substrate to form a source region; forming a channel region on said source region; forming a drain region on said channel region, wherein said drain region includes an extended drain region to provide a tunneling electrical field enhancement effect; forming a trench through said drain region and said channel region; forming a floating gate in said trench; and forming a control gate in operative relation to said floating gate.
Claim 3
Independent Claim
105 words
A method of forming a vertical memory cell comprising the steps of: doping a substrate to form a source region; forming a channel region on said source region; forming a drain region on said channel region; forming a conductive layer insulated from said drain region; forming a trench through said conductive layer, said drain region, and said channel region to said source region, thereby forming an erase/program gate from said conductive layer; forming a floating gate in operative relation to said erase/program gate, said drain region, said channel region, and said source region; and forming a control gate in operative relation to said floating gate.
Claim 4
Independent Claim
105 words
A method of forming a vertical memory cell comprising the steps of: doping a substrate to form a source region; forming a channel region on said source region; forming a drain region on said channel region; forming a conductive layer insulated from said drain region; forming a trench through said conductive layer, said drain region, and said channel region to said source region, thereby forming an erase/program gate from said conductive layer; forming a floating gate in operative relation to said erase/program gate, said drain region, said channel region, and said source region; and forming a control gate in operative relation to said floating gate.
Claim 5
Independent Claim
68 words
A method of forming a vertical memory cell, comprising: forming a first transistor in a first trench in a substrate; and forming a second transistor in a second trench in said substrate, said second transistor being connected in series with said first transistor in said memory cell, wherein said second trench is disposed in said first trench and extends deeper into said substrate than does said first trench.
Claim 6
Independent Claim
68 words
A method of forming a vertical memory cell, comprising: forming a first transistor in a first trench in a substrate; and forming a second transistor in a second trench in said substrate, said second transistor being connected in series with said first transistor in said memory cell, wherein said second trench is disposed in said first trench and extends deeper into said substrate than does said first trench.
Claim 7
Dependent Claim
97 words
The method of claim 3, further comprising: doping said substrate to form a source region; forming a channel region on said source region; forming a drain region on said channel region; forming said first trench through said drain region and a portion of said channel; forming a floating gate in said first trench; forming said second trench through a portion of said channel region to said source region; and forming a control gate in operative relation to said floating gate and said channel region, wherein said control gate is formed in said first and said second trenches.
Claim 8
Independent Claim
102 words
A method for forming a vertical memory cell, comprising: doping a substrate to form a channel region; depositing a conductive layer on said substrate to form a drain region; forming a first trench through said conductive layer and into said substrate; forming a floating gate on the sidewall of said first trench; forming a second trench in said substrate after forming said floating gate; doping said substrate to form a source region in said second trench; and forming a control gate in operative relation to said floating gate, wherein said control gate is disposed in said first trench and said second trench.
Claim 9
Independent Claim
102 words
A method for forming a vertical memory cell, comprising: doping a substrate to form a channel region; depositing a conductive layer on said substrate to form a drain region; forming a first trench through said conductive layer and into said substrate; forming a floating gate on the sidewall of said first trench; forming a second trench in said substrate after forming said floating gate; doping said substrate to form a source region in said second trench; and forming a control gate in operative relation to said floating gate, wherein said control gate is disposed in said first trench and said second trench.
Claim 10
Dependent Claim
22 words
The method of claim 5, wherein forming said second trench comprises forming said second trench at a bottom of said first trench.
Claim 11
Dependent Claim
35 words
The method of claim 4 further comprising forming a conductive layer insulated from said drain region, wherein said first trench is formed through said conductive layer, thereby forming an erase/program gate from said conductive layer.
Claim 12
Dependent Claim
46 words
The method of claim 3, wherein forming said first transistor comprises forming a floating gate transistor, and forming said second transistor comprises forming said second transistor so that said first and second transistors both modulate a single channel region and together form a split-gate memory cell.
Claim 13
Independent Claim
119 words
A method for forming an array of vertical memory cells comprising: forming a first layer of a semiconductor material having a conductivity type for forming channel regions of said memory cells; forming on said first layer, a second layer of a semiconductor material having a conductivity type for forming drain regions of said memory cells; patterning said second layer to form bit lines; forming bit line isolation regions between said bit lines and extending above said bit lines; forming spacers which are on sidewalls of said bit line isolation regions and overlying portions of said bit lines; and forming trenches through said bit lines and into said first layer, said trenches having sidewalls aligned with edges of said spacers.
Claim 14
Independent Claim
119 words
A method for forming an array of vertical memory cells comprising: forming a first layer of a semiconductor material having a conductivity type for forming channel regions of said memory cells; forming on said first layer, a second layer of a semiconductor material having a conductivity type for forming drain regions of said memory cells; patterning said second layer to form bit lines; forming bit line isolation regions between said bit lines and extending above said bit lines; forming spacers which are on sidewalls of said bit line isolation regions and overlying portions of said bit lines; and forming trenches through said bit lines and into said first layer, said trenches having sidewalls aligned with edges of said spacers.
Claim 15
Dependent Claim
33 words
The method of claim 9, further comprising forming a source region, wherein said first layer overlies said source region and forming said trenches creates openings through said first layer to said source region.
Claim 16
Dependent Claim
20 words
The method of claim 9, further comprising doping bottoms of said trenches to from source regions for said memory cells.
Claim 17
Dependent Claim
89 words
The method of claim 9, further comprising forming a third layer above said second semiconductor layer, wherein: patterning said second semiconductor layer comprises forming a photoresist mask above said third layer, and etching openings through said third layer and said second layer according to a pattern of said photoresist mask; forming said bit line isolation regions comprises filling said openings to a point approximately level with a top surface of said third layer; and selectively etching said third layer to create sidewall spacers on said bit line isolation regions.
Claim 18
Dependent Claim
32 words
The method of claim 12, wherein said third layer comprises phosphorous doped silicon dioxide, said bit line isolation comprises silicon dioxide, and said selective etch is selective to phosphorous doped silicon dioxide.
Claim 19
Dependent Claim
75 words
The method of claim 9, wherein forming each of said trenches comprises: forming a first trench in said first layer, wherein a sidewall of said first trench is aligned with an edge of one of said spacers; forming a floating gate on said sidewall of said first trench; and forming a second trench through a bottom surface of said first trench, said second trench having a sidewall aligned with an edge of said floating gate.
Claim 20
Dependent Claim
28 words
The method of claim 9, further comprising: forming third layer of a conductive material overlying said second layer; and patterning said third layer to form erase program gates.
Claim 21
Dependent Claim
69 words
The method of claim 15, wherein: patterning said second layer uses a mask which is also used when patterning said third layer; top surfaces of said bit line isolation regions are above a top surface of said third layer; said spacers overlie portions of said erase/program gates; and forming said trenches etches through said erase/program gates and aligns edges of said erase/program gates with said edges of said spacers.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-31 | 2000-09-30 | 2001-04-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-31 | 2004-09-30 | 2005-04-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-31 | 2008-09-30 | 2009-04-01 | $7700.00 | Window Closed / Lapsed |