US5614437A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fabricating reliable metallization with Ta-Si-N barrier for semiconductors
Assignee: Bell Semiconductor LLC
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Filing: 1995-01-26
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Granted: 1997-03-25
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Expires: 2015-01-26
Abstract
Abstract A method for manufacturing an ohmic contact on a semiconductor device, as disclosed herein, includes a first step of etching a via through a non-conductive layer formed over a partially fabricated version of the semiconductor device. This step exposes a region of a device element such as a source, gate electrode, etc. Next, an ohmic contact layer including tantalum and silicon is deposited over the partially fabricated device and in the vias by sputtering in an argon atmosphere. Thereafter, and in the same processing apparatus, a barrier layer including a tantalum silicon nitride is deposited over the ohmic contact layer. Then an aluminum alloy metallization layer is directly deposited on the partially fabricated device at a temperature of at least 650° C. At this deposition temperature, the metallization layer conformally fills the via, thereby producing a stable, uniform contact.
Inventors
- 👤 Ratan K. Choudhury
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 10:24
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10W20/033; H10W20/035; H10D; H10D62/00; H10D62/80; H10D62/83; H10D64/00; H10D64/60; H10D64/62; H10W20/40; H10W20/41; H10W20/425
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
165 words
A method for manufacturing a semiconductor device, said semiconductor device including a silicon substrate having at least one device element and a non-conductive layer at least partially covering said device element, said method comprising the steps of: etching a via extending through said non-conductive layer to said device element thereby providing an exposed region of said device element; depositing a tantalum silicide ohmic contact layer over at least a first portion of said non-conductive layer and said via, said ohmic contact layer being in electrical contact with said exposed region; depositing a tantalum silicon nitride barrier layer over at least a second portion of said non-conductive layer and said via, said barrier layer being in direct contact with said ohmic contact layer, and being in electrical contact with said exposed region; and depositing a metallization layer upon said semiconductor device, said metallization layer formed over and in electrical contact with said exposed region, and wherein said metallization layer is aluminum or an aluminum containing alloy.
Claim 2
Independent Claim
165 words
A method for manufacturing a semiconductor device, said semiconductor device including a silicon substrate having at least one device element and a non-conductive layer at least partially covering said device element, said method comprising the steps of: etching a via extending through said non-conductive layer to said device element thereby providing an exposed region of said device element; depositing a tantalum silicide ohmic contact layer over at least a first portion of said non-conductive layer and said via, said ohmic contact layer being in electrical contact with said exposed region; depositing a tantalum silicon nitride barrier layer over at least a second portion of said non-conductive layer and said via, said barrier layer being in direct contact with said ohmic contact layer, and being in electrical contact with said exposed region; and depositing a metallization layer upon said semiconductor device, said metallization layer formed over and in electrical contact with said exposed region, and wherein said metallization layer is aluminum or an aluminum containing alloy.
Claim 3
Dependent Claim
26 words
A method as recited in claim 1 wherein the step of depositing a metallization layer is performed at a temperature of at least about 650° C.
Claim 4
Dependent Claim
29 words
A method as recited in claim 1 wherein said step of depositing a metallization layer is performed under conditions such that said metallization layer has a planar upper surface.
Claim 5
Dependent Claim
21 words
A method as recited in claim 1 further comprising the step of depositing an anti-reflective layer formed over said metallization layer.
Claim 6
Dependent Claim
47 words
A method as recited in claim 1 further comprising the step of depositing a wetting layer upon said semiconductor device, said wetting layer formed over and in electrical contact with said exposed region whereby said wetting layer provides a surface that is relatively easily wettable by aluminum.
Claim 7
Dependent Claim
33 words
A method as recited in claim 5 further comprising the step of depositing a metallization layer upon said semiconductor device, said metallization layer formed over and in electrical contact with said exposed region.
Claim 8
Dependent Claim
20 words
A method as recited in claim 6 further comprising the step of depositing an anti-reflective layer on said metallization layer.
Claim 9
Dependent Claim
19 words
A method as recited in claim 1 wherein the step of etching is performed by a plasma etching method.
Claim 10
Dependent Claim
17 words
A method as recited in claim 1 wherein the step of etching is performed with diluted HF.
Claim 11
Dependent Claim
28 words
A method as recited in claim 1 wherein the deposition of said ohmic contact layer is performed by reactive sputtering of a tantalum-silicon target in an Ar plasma.
Claim 12
Dependent Claim
29 words
A method as recited in claim 10 wherein the deposition of said barrier layer is performed by reactive sputtering of the tantalum-silicon target in a N 2 /Ar plasma.
Claim 13
Independent Claim
178 words
A method for manufacturing a semiconductor device, said semiconductor device including a silicon substrate having at least one device element and a non-conductive layer at least partially covering said device element, said method comprising the steps of: etching a via extending through said non-conductive layer to said device element thereby providing an exposed region of said device element; depositing a tantalum silicide ohmic contact layer over at least a first portion of said non-conductive layer and said via, said ohmic contact layer being in electrical contact with said exposed region; depositing tantalum silicon nitride barrier layer over at least a second portion of said non-conductive layer and said via, said barrier layer being in direct contact with said ohmic contact layer, and being in electrical contact with said exposed region; and depositing a metallization layer on top of said tantalum silicon nitride barrier layer, whereby said tantalum silicon nitride layer acts as a barrier to transport of atoms from said metallization layer to said silicon substrate, and wherein said metallization layer is aluminum, or an aluminum containing alloy.
Claim 14
Independent Claim
178 words
A method for manufacturing a semiconductor device, said semiconductor device including a silicon substrate having at least one device element and a non-conductive layer at least partially covering said device element, said method comprising the steps of: etching a via extending through said non-conductive layer to said device element thereby providing an exposed region of said device element; depositing a tantalum silicide ohmic contact layer over at least a first portion of said non-conductive layer and said via, said ohmic contact layer being in electrical contact with said exposed region; depositing tantalum silicon nitride barrier layer over at least a second portion of said non-conductive layer and said via, said barrier layer being in direct contact with said ohmic contact layer, and being in electrical contact with said exposed region; and depositing a metallization layer on top of said tantalum silicon nitride barrier layer, whereby said tantalum silicon nitride layer acts as a barrier to transport of atoms from said metallization layer to said silicon substrate, and wherein said metallization layer is aluminum, or an aluminum containing alloy.
Claim 15
Dependent Claim
26 words
A method as recited in claim 12 wherein the step of depositing a metallization layer is performed at a temperature of at least about 650° C.
Claim 16
Dependent Claim
29 words
A method as recited in claim 12 wherein said step of depositing a metallization layer is performed under conditions such that said metallization layer has a planar upper surface.
Claim 17
Dependent Claim
21 words
A method as recited in claim 12 further comprising the step of depositing an anti-reflective layer formed over said metallization layer.
Claim 18
Dependent Claim
49 words
A method as recited in claim 12 further comprising the step of depositing a wetting layer upon said semiconductor device, said wetting layer formed over and in electrical contact with said exposed region whereby said wetting layer provides a surface that is relatively easily wettable by the metallization layer.
Claim 19
Dependent Claim
28 words
A method as recited in claim 12 wherein the deposition of said ohmic contact layer is performed by reactive sputtering of a tantalum-silicon target in an Ar plasma.
Claim 20
Dependent Claim
42 words
A method as recited in claim 17 wherein the deposition of said barrier layer is performed by adding nitrogen to the argon plasma after the ohmic contact layer has been formed whereby tantalum silicon nitride is deposited on said ohmic contact layer.
Claim 21
Dependent Claim
29 words
A method as recited in claim 12 wherein the deposition of said barrier layer is performed by reactive sputtering of a tantalum-silicon target in a N 2 /Ar plasma.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-24 | 2000-09-23 | 2001-03-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-24 | 2004-09-23 | 2005-03-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-24 | 2008-09-23 | 2009-03-25 | $7700.00 | Window Closed / Lapsed |