Chip stack and method of making same

Claim 2

An integrated circuit chip package comprising the combination of: a thin, small outline package comprised of an integrated circuit chip encapsulated in a plastic body of relatively thin, generally planar configuration and having leads extending from opposite ends of the plastic body and electrically coupled by wire bonds to contacts on the chip; and a relatively thin, generally planar frame having opposite, generally planar surfaces and having a central aperture therein defined by side walls thereof, the frame having a plurality of conductive pads disposed thereon adjacent an opposite pair of the side walls and electrically coupled to the leads extending from opposite ends of the plastic body to mount the thin, small outline package within the central aperture in the frame, and to support the thin, small outline package by the frame, the plastic body being spaced apart from the side walls of the central aperture and having opposite, generally planar surfaces which are generally coplanar with the opposite, generally planar surfaces of the frame.

Claim 3

An integrated circuit chip package in accordance with claim 1, wherein the opposite, generally planar surfaces of the frame define upper end lower surfaces thereof, the plurality of conductive pads are disposed on the upper surface of the frame, the frame has a plurality of outer edges extending between the upper and lower surfaces, and further including a second plurality of conductive pads mounted on the upper surface of the frame adjacent a plurality of the outer edges and coupled to selected ones of the leads and a third plurality of conductive pads mounted on the lower surface of the frame adjacent a plurality of the outer edges and coupled to selected ones of the leads.

Claim 4

An integrated circuit chip package in accordance with claim 2, wherein selected ones of the third plurality of conductive pads mounted on the lower surface of the frame are coupled to selected ones of the leads through vias extending through the frame between the upper and lower surfaces.

Claim 5

An integrated circuit chip package in accordance with claim 2, wherein the individual conductive pads of the second plurality of conductive pads are disposed directly opposite individual conductive pads of the third plurality of conductive pads, and selected ones of the second plurality of conductive pads are coupled to selected ones of the third plurality of conductive pads which are one position removed from the directly opposite conductive pad.

Claim 6

A chip stack comprising the combination of: a plurality of integrated circuit chip packages formed into a stack, each of the chip packages including an integrated circuit chip and a frame, said integrated circuit chip being mounted within said frame and said integrated circuit chip being electrically coupled to conductive pads on opposite upper and lower surfaces of the frame, the conductive pads on the upper surfaces of the frames of at least some of the plurality of chip packages being soldered to the conductive pads on the lower surface of the frames of at least some of the plurality of chip packages to hold the chip stack together and provide electrical interconnection between the chip packages, each of the plurality of integrated circuit chip packages, including the conductive pads on the opposite upper and lower surfaces of the frame thereof, being of identical configuration to the other chip packages in the stack and being individually addressable to the exclusion of the other chip packages in the stack.

Claim 7

A chip stack comprising the combination of: a plurality of integrated circuit chip packages formed into a stack, each of the chip packages including an integrated circuit chip and a frame, said integrated circuit chip being mounted within said frame and said integrated circuit chip being electrically coupled to conductive pads on opposite upper and lower surfaces of the frame, the conductive pads on the upper surfaces of the frames of at least some of the plurality of chip packages being soldered to the conductive pads on the lower surface of the frames of at least some of the plurality of chip packages to hold the chip stack together and provide electrical interconnection between the chip packages, each of the plurality of integrated circuit chip packages, including the conductive pads on the opposite upper and lower surfaces of the frame thereof, being of identical configuration to the other chip packages in the stack and being individually addressable to the exclusion of the other chip packages in the stack.

Claim 8

A chip stack in accordance with claim 1, further including a substrate mounting the plurality of chip packages thereon and electrically coupled to conductive pads on the lower surface of the frame of a bottom one of the plurality of chip packages.

Claim 9

A chip stack in accordance with claim 6, wherein the frames of the plurality of chip packages and the substrate are made of like, printed circuit board material, so that the frame of the bottom one of the plurality of chip packages and the substrate have like coefficients of thermal expansion.

Claim 10

A chip stack in accordance with claim 5, wherein, in each of the plurality of chip packages, the integrated circuit chip comprises a thin, small outline packaged chip disposed substantially completely within and spaced from the walls of a central aperture in the frame and having a plurality of leads at opposite ends thereof extending from the thin, small outline package and soldered to conductive pads on an upper surface of the frame so that the chip is supported by the frame.

Claim 11

A chip stack comprising the combination of: a plurality of integrated circuit chip packages formed into a stack and each including an integrated circuit chip mounted within a frame and electrically coupled to conductive pads on opposite upper and lower surfaces of the frame, the conductive pads on the upper surfaces of the frames of at least some of the plurality of chip packages being soldered to the conductive pads on the lower surface of the frames of at least some of the plurality of chip packages to hold the chip stack together and provide electrical interconnection between the chip packages, each of the plurality of integrated circuit chip packages, including the conductive pads on the opposite upper and lower surfaces of the frame thereof, being of identical configuration to the other chip packages in the stack and being individually addressable to the exclusion of the other chip packages in the stack; wherein the frames have conductive pads on the opposite upper and lower surfaces thereof arranged into a plurality of spaced apart columns along an edge of the chip stack, with each conductive pad on the upper surface of each frame lying within a column and being coupled through the frame to a conductive pad on the opposite lower surface of the frame and within an adjacent column, to form a stair step configuration of interconnected conductive pads at the edge of the chip stack, whereby the chip packages of identical configuration within the stack are individually addressable.

Claim 12

A chip stack comprising the combination of: a plurality of integrated circuit chip packages formed into a stack and each including an integrated circuit chip mounted within a frame and electrically coupled to conductive pads on opposite upper and lower surfaces of the frame, the conductive pads on the upper surfaces of the frames of at least some of the plurality of chip packages being soldered to the conductive pads on the lower surface of the frames of at least some of the plurality of chip packages to hold the chip stack together and provide electrical interconnection between the chip packages, each of the plurality of integrated circuit chip packages, including the conductive pads on the opposite upper and lower surfaces of the frame thereof, being of identical configuration to the other chip packages in the stack and being individually addressable to the exclusion of the other chip packages in the stack; wherein the frames have conductive pads on the opposite upper and lower surfaces thereof arranged into a plurality of spaced apart columns along an edge of the chip stack, with each conductive pad on the upper surface of each frame lying within a column and being coupled through the frame to a conductive pad on the opposite lower surface of the frame and within an adjacent column, to form a stair step configuration of interconnected conductive pads at the edge of the chip stack, whereby the chip packages of identical configuration within the stack are individually addressable.

Claim 13

A chip stack in accordance with claim 9, wherein the conductive pads on the lower surfaces of the frames within a given column are each coupled to a chip enable terminal of the integrated circuit chip mounted within the frame, whereby the chip packages of identical configuration. Within the stack may be individually enabled to the exclusion of the other chip packages in the stack.

Claim 16

A method of making a chip stack in accordance with claim 11, wherein the plurality of frames provided are of like material, and comprising the further steps of providing a substrate made of the like material of the plurality of frames and mounting the stack on the substrate.

Claim 17

A method of making a chip stack in accordance with claim 11, wherein the leads of each thin, small outline package are coupled to some of the conductive pads on the frame by soldering, and the conductive pads of adjacent ones of the frames are bonded together by dipping the edges of the stack of integrated circuit chip packages in solder.

Claim 18

A method of making a chip stack in accordance with claim 11, wherein the step of providing a plurality of frames includes arranging at least some of the plurality of conductive pads on opposite surfaces thereof to form columns of conductive pads generally parallel to each other and to one of the relatively flat side surfaces and coupling selected ones of the conductive pads on one of the opposite surfaces to conductive pads in adjacent ones of the columns and which are on the opposite one of the opposite surfaces.

Claim 19

A chip stack arrangement comprising the combination of: a plurality of integrated circuit chip packages having opposite, relatively flat surfaces disposed adjacent each other to form a stack thereof having a relatively flat upper surface formed by a relatively flat surface of an uppermost one of the chip packages and a relatively flat lower surface formed by a relatively flat surface of a lowermost one of the chip packages and being generally parallel to the upper surface, each of the packages having first and second pluralities of conductive pads mounted on the opposite, relatively flat surfaces thereof opposite each other and in contact with conductive pads of an adjacent package and coupled to an integrated circuit chip within the package, the plurality of chip packages being of like configuration and the first and second pluralities of conductive pads being arranged in like patterns on the plurality of chip packages, the first and second pluralities of conductive pads of the packages being arranged into a plurality of columns which are generally parallel to each other and generally perpendicular to the upper and lower surfaces, with a respective conductive pad in the first plurality of conductive pads of a package lying within one of the columns and being coupled to a conductive pad in the second plurality of conductive pads of the package lying within a column adjacent said one of the columns, whereby some of the conductive pads of the various packages are coupled together in stair step fashion at a relatively, flat edge of the chip stack which extends between and is generally perpendicular to the upper and lower surfaces, to provide for individual addressing of each of the chip packages of like configuration to the exclusion of other ones of the plurality of chip packages.

Claim 20

A chip stack arrangement comprising the combination of: a plurality of integrated circuit chip packages having opposite, relatively flat surfaces disposed adjacent each other to form a stack thereof having a relatively flat upper surface formed by a relatively flat surface of an uppermost one of the chip packages and a relatively flat lower surface formed by a relatively flat surface of a lowermost one of the chip packages and being generally parallel to the upper surface, each of the packages having first and second pluralities of conductive pads mounted on the opposite, relatively flat surfaces thereof opposite each other and in contact with conductive pads of an adjacent package and coupled to an integrated circuit chip within the package, the plurality of chip packages being of like configuration and the first and second pluralities of conductive pads being arranged in like patterns on the plurality of chip packages, the first and second pluralities of conductive pads of the packages being arranged into a plurality of columns which are generally parallel to each other and generally perpendicular to the upper and lower surfaces, with a respective conductive pad in the first plurality of conductive pads of a package lying within one of the columns and being coupled to a conductive pad in the second plurality of conductive pads of the package lying within a column adjacent said one of the columns, whereby some of the conductive pads of the various packages are coupled together in stair step fashion at a relatively, flat edge of the chip stack which extends between and is generally perpendicular to the upper and lower surfaces, to provide for individual addressing of each of the chip packages of like configuration to the exclusion of other ones of the plurality of chip packages.

Claim 21

A chip stack arrangement comprising the combination of: a plurality of integrated circuit chip packages having opposite, relatively flat surfaces disposed adjacent each other to form a stack thereof, each of the packages having first and second pluralities of conductive pads mounted on the opposite, relatively flat surfaces thereof opposite each other and in contact with conductive pads of an adjacent package and coupled to an integrated circuit chip within the package, the plurality of chip packages being of like configuration and the first and second pluralities of conductive pads being arranged in like patterns on the plurality of chip packages, the first and second pluralities of conductive pads of the packages being arranged into a plurality of relatively parallel columns with a respective conductive pad in the first plurality of conductive pads of a package lying within one of the columns and being coupled to a conductive pad in the second plurality of conductive pads of the package lying within a column adjacent said one of the columns, whereby some of the conductive pads of the various packages are coupled together in stair step fashion at an edge of the chip stack to provide for individual addressing of each of the chip packages of like configuration to the exclusion of other ones of the plurality of chip packages; wherein a respective conductive pad in the first plurality of conductive pads of a package lying within one of the columns is coupled to a conductive pad in the second plurality of conductive pads of the package lying within a column adjacent said one of the columns by a via extending through the package between the opposite, relatively flat surfaces thereof.

Claim 22

A chip stack arrangement comprising the combination of: a plurality of integrated circuit chip packages having opposite, relatively flat surfaces disposed adjacent each other to form a stack thereof, each of the packages having first and second pluralities of conductive pads mounted on the opposite, relatively flat surfaces thereof opposite each other and in contact with conductive pads of an adjacent package and coupled to an integrated circuit chip within the package, the plurality of chip packages being of like configuration and the first and second pluralities of conductive pads being arranged in like patterns on the plurality of chip packages, the first and second pluralities of conductive pads of the packages being arranged into a plurality of relatively parallel columns with a respective conductive pad in the first plurality of conductive pads of a package lying within one of the columns and being coupled to a conductive pad in the second plurality of conductive pads of the package lying within a column adjacent said one of the columns, whereby some of the conductive pads of the various packages are coupled together in stair step fashion at an edge of the chip stack to provide for individual addressing of each of the chip packages of like configuration to the exclusion of other ones of the plurality of chip packages; wherein a respective conductive pad in the first plurality of conductive pads of a package lying within one of the columns is coupled to a conductive pad in the second plurality of conductive pads of the package lying within a column adjacent said one of the columns by a via extending through the package between the opposite, relatively flat surfaces thereof.

Claim 23

A chip stack arrangement in accordance with claim 15, wherein within a given one of the columns, the conductive pad within the second plurality of conductive pads of each package is coupled to a chip enable terminal of the integrated circuit chip of the package to provide for individual enabling of each of the chip packages of like configuration to the exclusion of other ones of the plurality of chip packages.

Claim 24

A chip stack arrangement in accordance with claim 17, further including a substrate coupled to the chip stack and having a plurality of spaced apart chip enable conductive pads on a surface thereof in contact with different ones of spaced apart conductive pads on the lower surface of the stack formed by a relatively flat surface of a lowermost one of the chip packages.