IR FM modem with flash modulation

Claim 2

In a Biphase or FM modulation system including means for FM encoding a digital input signal by producing an FM encoded output signal comprising HIGH levels and LOW levels, having lengths of no less than half a bit cell period and no more than one bit cell period, indicative of transitions in said digital input signal, the improvement comprising: means, responsive to said FM encoded output signal, for Flash modulating said FM encoded output signal by producing pulses of less than half a bit cell width in accordance with the levels of said FM encoded output signal in each half bit cell period, said means for Flash modulating comprising: counter means, responsive to the receipt of a HIGH level of said FM encoded output signal, for outputting count pulses including a first count pulse and a fifth count pulse; first means, responsive to the first count pulse from said counter means, for outputting a pulse signal; and second means, responsive to the fifth count pulse, for ceasing said pulse signal output by said first means.

Claim 3

A system as in claim 1 wherein said means for Flash modulating comprises means for producing pulses of about 1/4 bit cell widths.

Claim 4

A system as in claim 1 wherein said counter means outputs a ninth count pulse and a thirteenth count pulse, and said first means outputs a pulse signal in response to the ninth count pulse; and said second means, in response to the thirteenth count pulse, ceases said pulse signal output by said first means.

Claim 5

A system as in claim 1 wherein said counter means outputs a third count pulse and an eleventh count pulse, and comprises: means for sensing the beginning of a HIGH level of said FM encoded output signal, and outputting a signal to start said count pulses; and further comprising means for resetting said sensing means in response to the third and eleventh count pulses.

Claim 6

A system as in claim 1 further comprising: means for sensing a LOW level of said FM encoded output signal and producing a signal indicative of the sensing of a LOW level of said FM encoded output signal; and means, responsive to said signal indicative of the sensing of a LOW level of said FM encoded output signal, for resetting said counter means to zero.

Claim 7

A system as in claim 1 further comprising means for demodulating said Flash modulated pulse signals comprising: means for receiving incoming Flash modulated pulses from said Flash modulating means; and means, responsive to the receipt of an incoming Flash modulated pulse by said receiving means, for outputting a half bit cell width signal upon the sensing thereof.

Claim 8

A system as in claim 6 wherein said outputting means comprises: counter means for outputting count pulses; and first means, responsive to the third count pulse and the eleventh count pulse from said counter means, for sampling said receiving means for an incoming Flash modulated pulse and outputting a half bit cell width signal upon the sensing thereof.

Claim 9

A system as in claim 7 wherein said means for demodulating further comprises: second means, responsive to the fourth count pulse from said counter means, for sampling the output of said first means and resetting said counter means to zero when no half bit cell width signal is sensed.

Claim 10

A system as in claim 8 wherein said second means comprises means for sampling the output of said first means in response to the twelfth count pulse from said counter means, and for resetting said counter means to zero when no half bit cell width signal is sensed.

Claim 11

A system as in claim 1 further comprising means for converting the pulses produced by said means for Flash modulating to IR light pulse signals.

Claim 12

In a Biphase or FM modulation system including means for FM encoding a digital input signal by producing an FM encoded output signal comprising HIGH levels and LOW levels, having lengths of no less than half a bit cell period and no more than one bit cell period, indicative of transitions in said digital input signal, the improvement comprising: means, responsive to said FM encoded output signal, for Flash modulating said FM encoded output signal by producing pulses of less than half a bit cell width in accordance with the levels of said FM encoded output signal in each half bit cell period; and means for demodulating said Flash modulated pulse signals comprising: means for receiving incoming Flash modulated pulses from said means for Flash modulating; and means, responsive to the receipt of an incoming Flash modulated pulse by said receiving means, for outputting a half bit cell width signal, said means for outputting comprising: counter means for outputting count pulses including a third, a fourth, an eleventh, and a twelfth count pulse; and first means, responsive to the third count pulse and the eleventh count pulse from said counter means, for sampling said receiving means for an incoming Flash modulated pulse and outputting a half bit cell width signal.

Claim 13

In a Biphase or FM modulation system including means for FM encoding a digital input signal by producing an FM encoded output signal comprising HIGH levels and LOW levels, having lengths of no less than half a bit cell period and no more than one bit cell period, indicative of transitions in said digital input signal, the improvement comprising: means, responsive to said FM encoded output signal, for Flash modulating said FM encoded output signal by producing pulses of less than half a bit cell width in accordance with the levels of said FM encoded output signal in each half bit cell period; and means for demodulating said Flash modulated pulse signals comprising: means for receiving incoming Flash modulated pulses from said means for Flash modulating; and means, responsive to the receipt of an incoming Flash modulated pulse by said receiving means, for outputting a half bit cell width signal, said means for outputting comprising: counter means for outputting count pulses including a third, a fourth, an eleventh, and a twelfth count pulse; and first means, responsive to the third count pulse and the eleventh count pulse from said counter means, for sampling said receiving means for an incoming Flash modulated pulse and outputting a half bit cell width signal.

Claim 14

A system as in claim 11 wherein said means for demodulating further comprises: second means, responsive to the fourth count pulse from said counter means, for sampling the output of said first means and resetting said counter means to zero when no half bit cell width signal is sensed.

Claim 15

A system as in claim 12 wherein said second means comprises means for sampling the output of said first means in response to the twelfth count pulse from said counter means, and for resetting said counter means to zero when no half bit cell width signal is sensed.

Claim 16

A system as in claim 11 further comprising means for converting the pulses produced by said means for Flash modulating to IR pulse signals.

Claim 17

In a Biphase or FM modulation process involving FM encoding a digital input signal by producing an FM encoded output signal comprising HIGH levels and LOW levels, having lengths of no less than half a bit cell period and no more than a bit cell period, indicative of transitions in said digital input signal, the method comprising the steps of: receiving said FM encoded output signal; and Flash modulating said FM encoded output signal by producing pulses of less than half a bit cell width in accordance with transitions in the levels of said FM encoded output signal in each half bit cell period, said Flash modulating step comprising: outputting count pulses in response to the receipt of a HIGH level of said FM encoded output signal, including a first, a third, a fifth, a ninth, an eleventh, and a thirteenth count pulse; outputting a pulse signal in response to the receipt of the first count pulse; and ceasing the outputting of said pulse signal in response to the fifth count pulse.

Claim 18

In a Biphase or FM modulation process involving FM encoding a digital input signal by producing an FM encoded output signal comprising HIGH levels and LOW levels, having lengths of no less than half a bit cell period and no more than a bit cell period, indicative of transitions in said digital input signal, the method comprising the steps of: receiving said FM encoded output signal; and Flash modulating said FM encoded output signal by producing pulses of less than half a bit cell width in accordance with transitions in the levels of said FM encoded output signal in each half bit cell period, said Flash modulating step comprising: outputting count pulses in response to the receipt of a HIGH level of said FM encoded output signal, including a first, a third, a fifth, a ninth, an eleventh, and a thirteenth count pulse; outputting a pulse signal in response to the receipt of the first count pulse; and ceasing the outputting of said pulse signal in response to the fifth count pulse.

Claim 19

A method as in claim 15 wherein said Flash modulating step comprises producing pulses of about 1/4 bit cell widths.

Claim 20

A method as in claim 15 comprising the further steps of: outputting a pulse signal in response to the ninth count pulse; and ceasing said pulse signal output in response to the thirteenth count pulse.

Claim 21

A method as in claim 15 comprising the further steps of: outputting a signal to start said count pulses upon the sensing of the beginning of a HIGH level of said FM encoded output signal; and resensing the level of said FM encoded output signal in response to the third and eleventh count pulses.

Claim 22

A method as in claim 15 further comprising the steps of: sensing a LOW level of said FM encoded output signal and producing a signal indicative of the sensing of a LOW level of said FM encoded output signal; and resetting said counter means to zero in response to said signal indicative of the sensing of a LOW level of said FM encoded output signal.

Claim 23

A method as in claim 15 further comprising demodulating said Flash modulated pulse signals by the steps of: receiving incoming Flash modulated pulses; and outputting a half bit cell width signal in response to the receipt of an incoming Flash modulated pulse.

Claim 24

A method as in claim 20 comprising the further steps of: outputting count pulses in response to the receipt of an incoming Flash modulated pulse; sampling for the receipt of an incoming Flash modulated pulse in response to the third and eleventh count pulses; and outputting a half bit cell width signal upon the sensing thereof.

Claim 25

A method as in claim 21 further comprising the steps of: responsive to the fourth count pulse, sampling for the output of a half bit cell width signal; and resetting the count pulses to zero when no half bit cell width signal is sensed.

Claim 26

A method as in claim 22 further comprising the steps of: sampling for the output of a half bit cell width signal in response to the twelfth count pulse; and resetting said count pulses to zero when no half bit cell width signal is sensed.

Claim 27

A method as in claim 15 further comprising the step of converting said Flash modulated pulses of less than a half bit cell width to IR light pulse signals.

Claim 28

In a Biphase or FM modulation process involving FM encoding a digital input signal by producing an FM encoded output signal comprising HIGH levels and LOW levels, having lengths of no less than half a bit cell period and no more than a bit cell period, indicative of transitions in said digital input signal, the method comprising the steps of: receiving said FM encoded output signal; and Flash modulating said FM encoded output signal by producing pulses of less than half a bit cell width in accordance with transitions in the levels of said FM encoded output signal in each half bit cell period; and receiving said Flash modulated pulses of less than half a bit cell width; outputting a half bit cell width signal in response to the receipt of a Flash modulated pulse of less than half a bit cell width; outputting count pulses in response to the receipt of a Flash modulated pulse of less than half a bit cell width, including a third, a fourth, and an eleventh count pulse; sampling for the receipt of an incoming Flash modulated pulse of less than half a bit cell width in response to the third and eleventh count pulses; and outputting a half bit cell width signal upon the sensing of a Flash modulated pulse of less than half a bit cell width.

Claim 29

In a Biphase or FM modulation process involving FM encoding a digital input signal by producing an FM encoded output signal comprising HIGH levels and LOW levels, having lengths of no less than half a bit cell period and no more than a bit cell period, indicative of transitions in said digital input signal, the method comprising the steps of: receiving said FM encoded output signal; and Flash modulating said FM encoded output signal by producing pulses of less than half a bit cell width in accordance with transitions in the levels of said FM encoded output signal in each half bit cell period; and receiving said Flash modulated pulses of less than half a bit cell width; outputting a half bit cell width signal in response to the receipt of a Flash modulated pulse of less than half a bit cell width; outputting count pulses in response to the receipt of a Flash modulated pulse of less than half a bit cell width, including a third, a fourth, and an eleventh count pulse; sampling for the receipt of an incoming Flash modulated pulse of less than half a bit cell width in response to the third and eleventh count pulses; and outputting a half bit cell width signal upon the sensing of a Flash modulated pulse of less than half a bit cell width.

Claim 30

A method as in claim 25 further comprising the steps of: responsive to the fourth count pulse, sampling for said outputting of a half bit cell width signal; and resetting the count pulses to zero when no half bit cell width signal is sensed.

Claim 31

A method as in claim 26 further comprising the steps of: sampling for said outputting of a half bit cell width signal in response to the twelfth count pulse; and resetting said count pulses to zero when no half bit cell width signal is sensed.

Claim 32

A method as in claim 25 further comprising the step of converting said Flash modulated pulses of less than a half bit cell width to IR pulse signals.