US5289141A
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Method and apparatus for digital modulation using concurrent pulse addition and subtraction
Assignee: Motorola Solutions Inc
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Filing: 1992-10-13
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Granted: 1994-02-22
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Expires: 2012-10-13
Abstract
Abstract A method and apparatus for generating an output signal (616) having a pre-determined frequency shift relative to the frequency of a reference signal from a reference frequency generator (202) comprise a digital phase-locked loop (206) coupled to the reference signal for generating the output signal (616). The method and apparatus further comprise adding pulses to the reference signal in a pulse addition circuit (304), the pulses recurring at a first cyclical rate determined by a microprocessor (702). The method and apparatus further comprise concurrently subtracting pulses from the reference signal in a pulse subtraction circuit (302) at a second cyclical rate.
Inventors
- 👤 Peter Nanni
- 👤 Bradley M. Hiben
- 👤 Leslie D. Mutz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 21:14
CPC Classifications
H; H03; H03C; H03C3/00; H03C3/02; H03C3/09; H03C3/0908; H03C3/0966
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
73 words
A method of generating an output signal having a pre-determined frequency shift relative to the frequency of a reference signal in a system comprising a digital phase-locked loop coupled to the reference signal for generating the output signal, the method comprising the steps of: (a) adding pulses to the reference signal, the pulses recurring at a first cyclical rate; and (b) concurrently subtracting pulses from the reference signal at a second cyclical rate.
Claim 2
Independent Claim
73 words
A method of generating an output signal having a pre-determined frequency shift relative to the frequency of a reference signal in a system comprising a digital phase-locked loop coupled to the reference signal for generating the output signal, the method comprising the steps of: (a) adding pulses to the reference signal, the pulses recurring at a first cyclical rate; and (b) concurrently subtracting pulses from the reference signal at a second cyclical rate.
Claim 3
Dependent Claim
36 words
The method in accordance with claim 1, further comprising the step of (c) selecting the first and second cyclical rates to be greater than a rate determined by frequency response characteristics of the digital phase-locked loop.
Claim 4
Dependent Claim
27 words
The method in accordance with claim 1, wherein step (b) further comprises the step of (d) preventing a pulse subtraction from occurring simultaneously with a pulse addition.
Claim 5
Dependent Claim
53 words
The method in accordance with claim 1, further comprising the step of (e) selecting the first and second cyclical rates such that the arithmetic difference between the first and second rates is equal to the pre-determined frequency shift of the output signal divided by a frequency multiplying factor of the digital phase-locked loop.
Claim 6
Dependent Claim
24 words
The method in accordance with claim 1, further comprising the step of (f) synchronizing the first and second cyclical rates with the reference signal.
Claim 7
Dependent Claim
54 words
The method in accordance with claim 1, further comprising the step of (g) selecting the first and second cyclical rates such that first and second signals having the first and second cyclical rates will traverse an integer divisor of three-hundred-sixty degrees of phase difference relative to one another per cycle of the first signal.
Claim 8
Dependent Claim
34 words
The method in accordance with claim 6, further comprising the step of (h) selecting initial phase offset between the first and second signals to be one-half of the integer divisor determined in step (g).
Claim 9
Dependent Claim
34 words
The method in accordance with claim 6, further comprising the step of (i) selecting initial phase offset between the first and second signals to be one-quarter of the integer divisor determined in step (g).
Claim 10
Independent Claim
84 words
An apparatus for generating an output signal having a pre-determined frequency shift relative to the frequency of a reference signal in a system comprising a digital phase-locked loop coupled to the reference signal for generating the output signal, the apparatus comprising: pulse addition means coupled to the reference signal for adding pulses recurring at a first cyclical rate to the reference signal; and pulse subtraction means coupled to the reference signal for concurrently subtracting pulses at a second cyclical rate from the reference signal.
Claim 11
Independent Claim
84 words
An apparatus for generating an output signal having a pre-determined frequency shift relative to the frequency of a reference signal in a system comprising a digital phase-locked loop coupled to the reference signal for generating the output signal, the apparatus comprising: pulse addition means coupled to the reference signal for adding pulses recurring at a first cyclical rate to the reference signal; and pulse subtraction means coupled to the reference signal for concurrently subtracting pulses at a second cyclical rate from the reference signal.
Claim 12
Dependent Claim
48 words
The apparatus in accordance with claim 9 further comprising first processing means coupled to the pulse addition means and to the pulse subtraction means for selecting the first and second cyclical rates to be greater than a rate determined by frequency response characteristics of the digital phase-locked loop.
Claim 13
Dependent Claim
44 words
The apparatus in accordance with claim 9 further comprising second processing means coupled to the pulse addition means and to the pulse subtraction means for determining values and phasing of the first and second cyclical rates to prevent simultaneous pulse addition and pulse subtraction.
Claim 14
Dependent Claim
65 words
The apparatus in accordance with claim 9 further comprising third processing means coupled to the pulse addition means and to the pulse subtraction means for selecting the first and second cyclical rates such that the arithmetic difference between the first and second rates is equal to the pre-determined frequency shift of the output signal divided by a frequency multiplying factor of the digital phase-locked loop.
Claim 15
Dependent Claim
66 words
The apparatus in accordance with claim 9 further comprising fourth processing means coupled to the pulse addition means and to the pulse subtraction means for selecting the first and second cyclical rates such that first and second signals having the first and second cyclical rates will traverse an integer divisor of three-hundred-sixty degrees of phase difference relative to one another per cycle of the first signal.
Claim 16
Dependent Claim
35 words
The apparatus in accordance with claim 13 further comprising fifth processing means coupled to the pulse addition means and to the pulse subtraction means for selecting initial phase offset between the first and second signals.
Claim 17
Dependent Claim
91 words
A wireless communication transmitter comprising a frequency synthesizer for generating an output signal having a pre-determined frequency shift relative to the frequency of a reference signal in the synthesizer comprising a digital phase-locked loop coupled to the reference signal for generating the output signal, the frequency synthesizer comprising: a pulse adder coupled to the reference signal for adding pulses recurring at a first cyclical rate to the reference signal; and a pulse subtracter coupled to the reference signal for concurrently subtracting pulses at a second cyclical rate from the reference signal.
Claim 18
Dependent Claim
91 words
A wireless communication transmitter comprising a frequency synthesizer for generating an output signal having a pre-determined frequency shift relative to the frequency of a reference signal in the synthesizer comprising a digital phase-locked loop coupled to the reference signal for generating the output signal, the frequency synthesizer comprising: a pulse adder coupled to the reference signal for adding pulses recurring at a first cyclical rate to the reference signal; and a pulse subtracter coupled to the reference signal for concurrently subtracting pulses at a second cyclical rate from the reference signal.
Claim 19
Dependent Claim
49 words
The wireless communication transmitter in accordance with claim 15 further comprising a first processing element coupled to the pulse adder and to the pulse subtracter for selecting the first and second cyclical rates to be greater than a rate determined by frequency response characteristics of the digital phase-locked loop.
Claim 20
Dependent Claim
45 words
The wireless communication transmitter in accordance with claim 15 further comprising a second processing element coupled to the pulse adder and to the pulse subtracter for determining values and phasing of the first and second cyclical rates to prevent simultaneous pulse addition and pulse subtraction.
Claim 21
Dependent Claim
67 words
The wireless communication transmitter in accordance with claim 15 further comprising a third processing element coupled to the pulse adder and to the pulse subtracter for selecting the first and second cyclical rates such that the arithmetic difference between the first and second cyclical rates is equal to the predetermined frequency shift of the output signal divided by a frequency multiplying factor of the digital phase-locked loop.
Claim 22
Dependent Claim
67 words
The wireless communication transmitter in accordance with claim 15 further comprising a fourth processing element coupled to the pulse adder and to the pulse subtracter for selecting the first and second cyclical rates such that first and second signals having the first and second cyclical rates will traverse an integer divisor of three-hundred-sixty degrees of phase difference relative to one another per cycle of the first signal.
Claim 23
Dependent Claim
36 words
The wireless communication transmitter in accordance with claim 19 further comprising a fifth processing element coupled to the pulse adder and to the pulse subtracter for selecting initial phase offset between the first and second signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-21 | 1997-08-23 | 1998-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-21 | 2001-08-23 | 2002-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-21 | 2005-08-23 | 2006-02-22 | $7700.00 | Window Closed / Lapsed |