Controlled delay circuit

Claim 2

A signal delay circuit comprising: at least one delay cell, said at least one delay cell including first and second field-effect transistors, each of said first and second field-effect transistors having a source, a drain, a channel between the source and drain, and a control gate overlying the channel, the first and second field-effect transistors being of opposite channel conductivity types, the control gates of said first and second field-effect transistors being connected to each other, the drains of said first and second field-effect transistors being connected to each other, an input terminal connected to a node in the conncetion between the control gates of said first and second field-effect transistors, a current source having first and second terminals and being connected between the drains of said first and second terminals and field-effect transistors at said first and second terminals, an inverter having an input and an output, the input of said inverter being connected to one of said first and second terminals of said current source dependent upon whether the delay is to affect the leading edge or trailing edge of the signal to be delayed, and a capacitor connected between the input of said inverter and ground, said capacitor defining a delay time for the signal to be delayed proportional to the power supply voltage and inversely proportional to the current delivered by said current source; and a control circuit operably connected to said current source for regulating the current delivered by said current source so as to make the current proportional to the power supply voltage.

Claim 3

A signal delay circuit as set forth in claim 1, wherein said current source connected between the drains of said first and second field-effect transistors includes first and second field-effect transistors respectively having a source, a drain, a channel between the source and drain, and a control gate overlying the channel, the first and second field-effect transistors of said current source being arranged to define a current mirror in which the control gates of said first and second field-effect transistors included in said current source are connected together, and the source and drain of said first field-effect transistor included in said current source being connected between the drains of said first and second field-effect transistors of said at least one delay cell, and said control circuit having an output connected to said second field-effect transistor of said current source and providing a current proportional to the power supply voltage of the signal delay circuit to be copied by said current source.

Claim 4

A signal delay circuit comprising: at least one delay cell, said at least one delay cell including first and second field-effect transistors, each of said first and second field-effect transistors having a source, a drain, a channel between the source and drain, and a control gate overlying the channel, the first and second field-effect transistors being of opposite channel conductivity types, the control gates of said first and second field-effect transistors being connected to each other, the drains of said first and second field-effect transistors being connected to each other, an input terminal connected to a node in the connection between the control gates of said first and second field-effect transistors, a current source having first and second terminals and being connected between the drains of said first and second field-effect transistors at said first and second terminals, an inverter having an input and an output, the input of said inverter being connected to one of said first and second terminals of said current source dependent upon whether the delay is to affect the leading edge or trailing edge of the signal to be delayed, and a capacitor connected between the input of said inverter and ground, said capacitor defining a delay time for the signal to be delayed proportional to the power supply voltage and inversely proportional to the current delivered by said current source, and a control circuit operably connected to said current source for regulating the current delivered by said current source so as to make the current proportional to the power supply voltage, said control circuit including voltage generating means for generating a voltage during a first clock signal having a predetermined relationship with the current delivered by said current source, and comparison means for comparing the voltage linked to the current as delivered by said current source with a selected fraction of the power supply voltage during a second clock signal complementary to the first clock signal, said comparison means producing an error signal as an output for regulating said current source such that the voltage linked to the current delivered by said current source and the said fraction of the power supply voltage are substantially equal.

Claim 5

A signal delay circuit comprising: at least one delay cell, said at least one delay cell including first and second field-effect transistors, each of said first and second field-effect transistors having a source, a drain, a channel between the source and drain, and a control gate overlying the channel, the first and second field-effect transistors being of opposite channel conductivity types, the control gates of said first and second field-effect transistors being connected to each other, the drains of said first and second field-effect transistors being connected to each other, an input terminal connected to a node in the connection between the control gates of said first and second field-effect transistors, a current source having first and second terminals and being connected between the drains of said first and second field-effect transistors at said first and second terminals, an inverter having an input and an output, the input of said inverter being connected to one of said first and second terminals of said current source dependent upon whether the delay is to affect the leading edge or trailing edge of the signal to be delayed, and a capacitor connected between the input of said inverter and ground, said capacitor defining a delay time for the signal to be delayed proportional to the power supply voltage and inversely proportional to the current delivered by said current source, and a control circuit operably connected to said current source for regulating the current delivered by said current source so as to make the current proportional to the power supply voltage, said control circuit including voltage generating means for generating a voltage during a first clock signal having a predetermined relationship with the current delivered by said current source, and comparison means for comparing the voltage linked to the current as delivered by said current source with a selected fraction of the power supply voltage during a second clock signal complementary to the first clock signal, said comparison means producing an error signal as an output for regulating said current source such that the voltage linked to the current delivered by said current source and the said fraction of the power supply voltage are substantially equal.

Claim 6

A signal delay circuit as set forth in claim 3, wherein said voltage generating means comprises first and second capacitors connected in parallel to said current source, a clock-controlled switch interposed in the connection between said first and second capacitors and said current source and being responsive to the first clock signal, and said first capacitor of said voltage generating means fixing the current as delivered by said current source, said second capacitor of said voltage generating means being of smaller capacitance than said first capacitor and establishing the voltage to be compared with said fraction of the power supply voltage.

Claim 7

A signal delay circuit as set forth in claim 4, wherein said comparison means for comparing the voltage linked to the current as delivered by said current source with said fraction of the power supply voltage comprises a third capacitor connected in parallel with said second capacitor, a second clock-controlled switch interposed in the connection between said second and third capacitors and being responsive to the second clock signal, a third clock-controlled switch connected between said first capacitor and ground and being responsive to the second clock signal for short-circuiting said first capacitor, and a differential amplifier having first and second inputs for comparing said fraction of the power supply voltage with a voltage resulting from a redistribution of charge between said second capacitor and said third capacitor during the second clock signal.

Claim 8

An anti-overlap two-phase clock generator comprising: first and second delay cells, each of said delay cells including first and second field-effect transistors, each of said first and second field-effect transistors having a source, a drain, a channel between the source and drain, and a control gate overlying the channel, the first and second field-effect transistors being of opposite channel conductivity types, the control gates of said first and second field-effect transistors being connected to each other, the drains of said first and second field-effect transistors being connected to each other, an input terminal connected to a node in the connection between the control gates of said first and second field-effect transistors, a current source having first and second terminals and being connected between the drains of said first and second field-effect transistors at said first and second terminals, an inverter having an input and an output, the input of said inverter being connected to one of said first and second terminals of said current source dependent upon whether the delay is to affect the leading edge or trailing edge of the signal to be delayed, and a capacitor connected between the input of said inverter and ground, said capacitor defining a delay time for the signal to be delayed proportional to the power supply voltage and inversely proportional to the current delivered by said current source; a control circuit common to said first and second delay cells and being respectively operably connected to the current source of each of said first and second delay cells for regulating the current delivered by the respective current source so as to make the current proportional to the power supply voltage; first and second logic means having respective first and second inputs and an output, said first and second logic means respectively receiving a clock input signal and an inverted clock input signal at the first inputs thereof; the outputs of said first and second logic means being respectively connected to corresponding input terminals of said first and second delay cells; and the output of said first delay cell being connected to the second input of said second logic means and the output of said second delay cell being connected to the second input of said first logic means.

Claim 9

An anti-overlap two-phase clock generator comprising: first and second delay cells, each of said delay cells including first and second field-effect transistors, each of said first and second field-effect transistors having a source, a drain, a channel between the source and drain, and a control gate overlying the channel, the first and second field-effect transistors being of opposite channel conductivity types, the control gates of said first and second field-effect transistors being connected to each other, the drains of said first and second field-effect transistors being connected to each other, an input terminal connected to a node in the connection between the control gates of said first and second field-effect transistors, a current source having first and second terminals and being connected between the drains of said first and second field-effect transistors at said first and second terminals, an inverter having an input and an output, the input of said inverter being connected to one of said first and second terminals of said current source dependent upon whether the delay is to affect the leading edge or trailing edge of the signal to be delayed, and a capacitor connected between the input of said inverter and ground, said capacitor defining a delay time for the signal to be delayed proportional to the power supply voltage and inversely proportional to the current delivered by said current source; a control circuit common to said first and second delay cells and being respectively operably connected to the current source of each of said first and second delay cells for regulating the current delivered by the respective current source so as to make the current proportional to the power supply voltage; first and second logic means having respective first and second inputs and an output, said first and second logic means respectively receiving a clock input signal and an inverted clock input signal at the first inputs thereof; the outputs of said first and second logic means being respectively connected to corresponding input terminals of said first and second delay cells; and the output of said first delay cell being connected to the second input of said second logic means and the output of said second delay cell being connected to the second input of said first logic means.

Claim 10

An anti-overlap two-phase clock generator as set forth in claim 6, wherein said first and second logic means are NOR gates.

Claim 11

An anti-overlap two-phase clock generator as set forth in claim 7, wherein said control circuit common to said first and second delay cells includes voltage generating means for generating a voltage during a first clock signal having a predetermined relationship with the current delivered by said current source of each of said first and second delay cells, and comparison means for comparing the voltage linked to the current as delivered by said current source of each of said first and second delay cells with a selected fraction of the power supply voltage during a second clock signal complementary to the first clock signal, said comparison means producing an error signal as an output for regulating said current sources of each of said first and second delay cells such that the voltage linked to the current as delivered by said current sources of each of said first and second delay cells and the said fraction of the power supply voltage are substantially equal.