Master-slice type integrated circuit including macrocells associated with delay circuit

Claim 2

A master slice type integrated circuit including a macrocell connected to an input terminal so as to receive an input signal through said input terminal and execute a predetermined processing for the received input signal, a delay circuit connected to an output of the macrocell and composed of a plurality of unitary delay circuits located in parallel to one another and having predetermined but different delay times, one of said unitary delay circuits being composed of a simple wiring which will cause no substantial delay time, one of said unitary delay circuits being selected to be connected to the output of said macrocell, an output buffer having an input connected to an output of said selected unitary delay circuit and an output connected to an output terminal, so that the output of the macrocell is outputted through said output buffer with a desired delay time between said input terminal and said output terminal, said unitary delay circuits being other than the selected unitary delay circuit and are connected to neither the output of the corresponding macrocell nor the input of the corresponding output buffer.

Claim 3

A master slice type integrated circuit including a plurality of input terminals, a corresponding number of unitary circuits each having an input connected to a corresponding one of the plurality of input terminals and a corresponding number of output terminals each connected to an output of a corresponding one of the unitary circuits, each of the unitary circuits being composed of one macrocell connected to the corresponding input terminal so as to receive an input signal through the corresponding input terminal and executing a predetermined processing for the received input signal, a delay circuit connected to an output of the macrocell and composed of a plurality of unitary delay circuits located in parallel to one another and having predetermined but different delay times, one of said unitary delay circuits being composed of a simple wiring which will cause no substantial delay time, one of said unitary delay circuits being selected to be connected to the output of said macrocell, an output buffer having an input connected to an output of the selected unitary delay circuit and an output connected to the corresponding output terminal, so that the output of the macrocell of each unitary circuit is outputted through the corresponding output buffer with a desired delay time between the corresponding input terminal and the corresponding output terminal, said unitary delay circuits being other than the selected unitary delay circuit being connected to neither the corresponding macrocell nor the corresponding output buffer.

Claim 4

A master slice type integrated circuit including a plurality of input terminals, a corresponding number of unitary circuits each having an input connected to a corresponding one of the plurality of input terminals and a corresponding number of output terminals each connected to an output of a corresponding one of the unitary circuits, each of the unitary circuits being composed of one macrocell connected to the corresponding input terminal so as to receive an input signal through the corresponding input terminal and executing a predetermined processing for the received input signal, a delay circuit connected to an output of the macrocell and composed of a plurality of unitary delay circuits located in parallel to one another and having predetermined but different delay times, one of said unitary delay circuits being composed of a simple wiring which will cause no substantial delay time, one of said unitary delay circuits being selected to be connected to the output of said macrocell, an output buffer having an input connected to an output of the selected unitary delay circuit and an output connected to the corresponding output terminal, so that the output of the macrocell of each unitary circuit is outputted through the corresponding output buffer with a desired delay time between the corresponding input terminal and the corresponding output terminal, said unitary delay circuits being other than the selected unitary delay circuit being connected to neither the corresponding macrocell nor the corresponding output buffer.

Claim 5

A master slice type integrated circuit claimed in claim 2 wherein in each of the unitary circuits, the selected unitary delay circuit actually connected between the output of the corresponding macrocell and the input of the corresponding output buffer has a delay time minimizing a difference in an input terminal/output terminal delay time between the unitary circuits.

Claim 6

A master slice type integrated circuit claimed in claim 2 wherein in each of the unitary circuits, the selected unitary delay circuit actually connected between the output of the corresponding macrocell and the input of the corresponding output buffer has a delay time such that the input terminal/output terminal delay time of each of the unitary circuits gradually differs from one another.

Claim 7

A master slice type integrated circuit including at least one macrocell connected to an input terminal so as to receive an input signal through the input terminal and executing a predetermined processing for the received input signal, a delay circuit connected to an output of the macrocell and composed of a plurality of unitary delay circuits located in parallel to one another and having predetermined but different delay times, one of the unitary delay circuits being composed of a simple wiring which will cause no substantial delay time, all of the unitary delay circuits being connected to the output of the macrocell, a multiplexor receiving outputs of all said plurality of unitary delay circuits and an output buffer having an input connected to an output of the multiplexor and an output connected to an output terminal, the multiplexor being controlled by a control signal so as to output one selected from the output of said plurality of unitary delay circuits to the output buffer, so that the output of the macrocell is outputted through the output buffer with a desired delay time between the input terminal and the output terminal.

Claim 8

A master slice type integrated circuit including at least one macrocell connected to an input terminal so as to receive an input signal through the input terminal and executing a predetermined processing for the received input signal, a delay circuit connected to an output of the macrocell and composed of a plurality of unitary delay circuits located in parallel to one another and having predetermined but different delay times, one of the unitary delay circuits being composed of a simple wiring which will cause no substantial delay time, all of the unitary delay circuits being connected to the output of the macrocell, a multiplexor receiving outputs of all said plurality of unitary delay circuits and an output buffer having an input connected to an output of the multiplexor and an output connected to an output terminal, the multiplexor being controlled by a control signal so as to output one selected from the output of said plurality of unitary delay circuits to the output buffer, so that the output of the macrocell is outputted through the output buffer with a desired delay time between the input terminal and the output terminal.