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US5610084A
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Method of manufacturing an antifuse utilizing nitrogen implantation
Assignee: US Philips Corp
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Filing: 1995-06-07
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Granted: 1997-03-11
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Expires: 2015-06-07
Abstract
Abstract A method of manufacturing a programmable semiconductor element in the form of an anti-fuse, comprising a thin layer of silicon oxide between two electrode regions, such that a connection can be formed between these electrode regions through electric breakdown in the oxide. In the method, a nitrogen implantation is first carried out at the area of the oxide to be formed, so that a thin layer comprising nitrogen is formed at the surface, which has an oxidation-decelerating effect. Then the oxide is provided through thermal oxidation. Owing to the oxidation-decelerating effect of the layer with nitrogen, an extremely thin oxide layer, for example 5 nm thick, may be obtained in a reproducible manner in a sufficiently long oxidation time.
Inventors
- 👤 Jose Solo de Zaldivar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:43
CPC Classifications
H; H10; H10B; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10P; H10P14/00; H10P14/20; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P14/3424; H10P14/3426
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
111 words
A method of manufacturing a semiconductor device whereby a semiconductor body is provided at a surface with a programmable element in the form of an anti-fuse comprising a thin silicon oxide layer situated between a surface zone in the semiconductor body and an electrode applied on the silicon oxide layer, the anti-fuse being brought from a first, non-conducting state into a second, conducting state during programming in that a voltage is applied between the electrode and the surface zone, characterized in that the semiconductor body is doped with nitrogen at the area of the silicon oxide layer to be formed, after which the silicon oxide layer is formed through thermal oxidation.
Claim 2
Independent Claim
111 words
A method of manufacturing a semiconductor device whereby a semiconductor body is provided at a surface with a programmable element in the form of an anti-fuse comprising a thin silicon oxide layer situated between a surface zone in the semiconductor body and an electrode applied on the silicon oxide layer, the anti-fuse being brought from a first, non-conducting state into a second, conducting state during programming in that a voltage is applied between the electrode and the surface zone, characterized in that the semiconductor body is doped with nitrogen at the area of the silicon oxide layer to be formed, after which the silicon oxide layer is formed through thermal oxidation.
Claim 3
Dependent Claim
28 words
A method as claimed in claim 1, characterized in that the oxidation is continued until the silicon oxide layer has a thickness of at most approximately 8 nm.
Claim 4
Dependent Claim
28 words
A method as claimed in claim 2, characterized in that the oxidation is continued until the silicon oxide layer has a thickness of at most approximately 6 nm.
Claim 5
Dependent Claim
41 words
A method as claimed in claim 1, characterized in that the semiconductor body is doped by means of an implantation of nitrogen ions in a concentration which lies between 2×10 14 per cm 2 and 5×10 14 per cm 2 .
Claim 6
Dependent Claim
106 words
A method as claimed in claim 1, characterized in that the semiconductor body is also provided with a non-volatile memory element in the form of a field effect transistor with a floating gate which is locally separated from the surface of the semiconductor body by tunnel oxide, in that during the nitrogen doping the surface is masked against this doping at the area of the tunnel oxide to be provided, and in that simultaneously with the oxidation performed for obtaining the silicon oxide layer the tunnel oxide is provided to a thickness which is greater than the thickness of the silicon oxide layer of the anti-fuse.
Claim 7
Dependent Claim
44 words
A method as claimed in claim 5, characterized in that the oxidation is carried out such that the thickness of the tunnel oxide is approximately 10 nm and the thickness of the silicon oxide layer of the anti-fuse is at most approximately 6 nm.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-10 | 2000-09-09 | 2001-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-10 | 2004-09-09 | 2005-03-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-10 | 2008-09-09 | 2009-03-11 | $7700.00 | Window Closed / Lapsed |