Patent US5608867A successfully refreshed from Google Patents.
US5608867A
Expired / Lapsed
US
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Debugging system using virtual storage means, a normal bus cycle and a debugging bus cycle
Assignee: NEC Electronics Corp
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Filing: 1994-04-05
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Granted: 1997-03-04
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Expires: 2014-04-05
Abstract
Abstract A debugging system is adapted to perform debugging by employing a virtual address in a computer system which includes a microprocessor incorporating a virtual storage function and a function for outputting a normal bus cycle corresponding to a real address in a normal operation and a function for outputting a debugging bus cycle corresponding to a virtual address. The microprocessor outputs a signal indicative of a kind of access and a signal indicative of an outputting state of a virtual address during outputting of the virtual address in the debugging bus cycle. A memory device is connected to the microprocessor through an address bus and a data bus. The debugging system includes a bus monitoring means for monitoring output of the processor, the output from bus cycles and transfer data. The bus monitoring means includes a debugging means for performing the debugging process associated with the virtual address.
Inventors
- 👤 Toshinori Ishihara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 23:49
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3636; G06F11/364; G06F11/3648
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
496 words
A debugging system comprising: a microprocessor operatively connected to a data bus and an address bus, said microprocessor including virtual storage means operatively connected to said data bus and said address bus, said virtual storage means providing a virtual storage with a plurality of virtual addresses, said microprocessor for outputting a real address on said address bus during a normal bus cycle and for outputting a virtual address of said plurality of virtual addresses on said address bus during a debugging bus cycle, said microprocessor further outputting a first signal indicative of a kind of access and a second signal indicative of an outputting state of said virtual address on said data bus during outputting of said virtual address in said debugging bus cycle, said microprocessor outputting transfer data and other data signals on said data bus; a memory device connected to said microprocessor through said address bus and said data bus, for storing said transfer data and said other data in memory locations corresponding to said real address and said virtual address; and a bus monitoring device operatively connected to said data bus and said address bus, said bus monitoring device for monitoring, during the debugging bus cycle, said virtual address, said transfer data and said other data signals issued by said microprocessor. said bus monitoring device including a trace circuit operatively connected to said data bus and said address bus, said trace circuit for storing trace data including the virtual address and the transfer data, in order, when said second signal indicates an outputting state of the virtual address from said microprocessor, said trace circuit comprising virtual address selection output means operatively connected to said address virtual storage means, said virtual selection output means outputting said virtual address stored in virtual storage means to trace data storage means, included in said trace circuit on the basis of the first signal and the second signal, during the normal bus cycle, wherein said trace circuit comprises: trace data storage means operatively connected to said data bus and said address bus, said trace data storage means including virtual address storage means operatively connected to said microprocessor, said virtual address storage means storing said trace data; said virtual address storage means temporarily holding said virtual address output in said debugging cycle; setting means operatively connected to said virtual address storage means, said setting means being responsive to said first signal and said second signal, said setting means outputting a set signal to said virtual address storage means for controlling storing of said virtual address in said virtual address storage means; trace address outputting means operatively connected to said trace data storage means, said trace address outputting means generating an address for storing said trace data in said trace data storage means, during said normal bus cycle; and means for outputting an access signal operatively connected to said trace data storage means, said access signal outputting means controlling storage of said trace data into said trace data storage means.
Claim 2
Dependent Claim
496 words
A debugging system comprising: a microprocessor operatively connected to a data bus and an address bus, said microprocessor including virtual storage means operatively connected to said data bus and said address bus, said virtual storage means providing a virtual storage with a plurality of virtual addresses, said microprocessor for outputting a real address on said address bus during a normal bus cycle and for outputting a virtual address of said plurality of virtual addresses on said address bus during a debugging bus cycle, said microprocessor further outputting a first signal indicative of a kind of access and a second signal indicative of an outputting state of said virtual address on said data bus during outputting of said virtual address in said debugging bus cycle, said microprocessor outputting transfer data and other data signals on said data bus; a memory device connected to said microprocessor through said address bus and said data bus, for storing said transfer data and said other data in memory locations corresponding to said real address and said virtual address; and a bus monitoring device operatively connected to said data bus and said address bus, said bus monitoring device for monitoring, during the debugging bus cycle, said virtual address, said transfer data and said other data signals issued by said microprocessor. said bus monitoring device including a trace circuit operatively connected to said data bus and said address bus, said trace circuit for storing trace data including the virtual address and the transfer data, in order, when said second signal indicates an outputting state of the virtual address from said microprocessor, said trace circuit comprising virtual address selection output means operatively connected to said address virtual storage means, said virtual selection output means outputting said virtual address stored in virtual storage means to trace data storage means, included in said trace circuit on the basis of the first signal and the second signal, during the normal bus cycle, wherein said trace circuit comprises: trace data storage means operatively connected to said data bus and said address bus, said trace data storage means including virtual address storage means operatively connected to said microprocessor, said virtual address storage means storing said trace data; said virtual address storage means temporarily holding said virtual address output in said debugging cycle; setting means operatively connected to said virtual address storage means, said setting means being responsive to said first signal and said second signal, said setting means outputting a set signal to said virtual address storage means for controlling storing of said virtual address in said virtual address storage means; trace address outputting means operatively connected to said trace data storage means, said trace address outputting means generating an address for storing said trace data in said trace data storage means, during said normal bus cycle; and means for outputting an access signal operatively connected to said trace data storage means, said access signal outputting means controlling storage of said trace data into said trace data storage means.
Claim 3
Dependent Claim
91 words
A debugging system as set forth in claim 1, wherein said virtual address storage means comprises: instruction fetching page number storage means operatively connected to said virtual storage means, said instruction fetching page number storage means storing a first virtual page number for performing an instruction fetch from a plurality of virtual page numbers; and data accessing page number storage means operatively connected to said virtual storage means, said data accessing page number storage means storing a second virtual page number for accessing data from the plurality of virtual page numbers.
Claim 4
Dependent Claim
138 words
A debugging system as set forth in claim 1, wherein said virtual address storage means comprises: instruction fetching page number storage means operatively connected to said address virtual storage means, said instruction fetching page number storage means storing a first virtual page number for performing an instruction fetch from a plurality of virtual page numbers; and data accessing page number storage means operatively connected to said virtual storage means, said data accessing page number storage means storing a second virtual page number for accessing data from the plurality of virtual page numbers; said setting means storing said first virtual page number in said instruction fetching page number storage means when said first signal indicates instruction fetching and storing said second virtual page number in said data access page number storage means when said first signal indicates data access.
Claim 5
Dependent Claim
71 words
A debugging system as set forth in claim 3, wherein the virtual address selection output means outputs, to said trace data storage means, one of the first virtual page number, the second virtual page number and a third virtual page number, said third virtual page number corresponding to an access other than said instruction fetch and aid accessing data and corresponding to when said virtual address and said real address match.
Claim 6
Dependent Claim
423 words
A debugging system comprising: a microprocessor operatively connected to a data bus and an address bus, said microprocessor including virtual storage means operatively connected to said data bus and said address bus, said virtual storage means providing a virtual storage with a plurality of virtual addresses, said microprocessor for outputting a real address on said address bus during a normal bus cycle and for outputting a virtual address of said plurality of virtual addresses on said address bus during a debugging bus cycle; a memory device connected to said microprocessor through said address bus and said data bus for forming a system together with said microprocessor, for storing said transfer data and said other data in memory locations corresponding to said real address and said virtual address; a bus monitoring device connected to said microprocessor through the address bus and the data bus, said bus monitoring device for monitoring the debugging bus cycle, said bus monitoring device including a trap circuit operatively connected to said data bus and said address bus, said trap circuit for outputting a predetermined trap address and a trap demand signal to said microprocessor when said predetermined trap address matches said virtual address during the normal bus cycle, wherein said microprocessor outputs a first signal indicative of a kind of access and a second signal indicative of an outputting state of said virtual address on said data bus during outputting of said virtual address in said debugging bus cycle; and said trap circuit comprising: virtual address storage means operatively connected to said virtual storage means, said virtual address storage means temporarily storing said virtual address setting means operatively connected to said virtual address storage means, said setting means outputting a set signal for controlling storing of said virtual address into said virtual address storage means on the basis of the first signal and the second signal; trap address storage means operatively connected to said microprocessor, said trap address storage means setting said trap address for trapping said microprocessor; comparing means operatively connected to said virtual address storage means and said trap address storage means, said comparing means comparing the virtual address stored in said virtual address storage means and said trap address stored in said trap address storage means, during the normal bus cycle; and trap demand signal output means operatively connected to said comparing means, said trap demand signal output means outputting a trap demand signal to said microprocessor when said virtual address and said trap address match as a result of said comparing by said comparing means.
Claim 7
Dependent Claim
423 words
A debugging system comprising: a microprocessor operatively connected to a data bus and an address bus, said microprocessor including virtual storage means operatively connected to said data bus and said address bus, said virtual storage means providing a virtual storage with a plurality of virtual addresses, said microprocessor for outputting a real address on said address bus during a normal bus cycle and for outputting a virtual address of said plurality of virtual addresses on said address bus during a debugging bus cycle; a memory device connected to said microprocessor through said address bus and said data bus for forming a system together with said microprocessor, for storing said transfer data and said other data in memory locations corresponding to said real address and said virtual address; a bus monitoring device connected to said microprocessor through the address bus and the data bus, said bus monitoring device for monitoring the debugging bus cycle, said bus monitoring device including a trap circuit operatively connected to said data bus and said address bus, said trap circuit for outputting a predetermined trap address and a trap demand signal to said microprocessor when said predetermined trap address matches said virtual address during the normal bus cycle, wherein said microprocessor outputs a first signal indicative of a kind of access and a second signal indicative of an outputting state of said virtual address on said data bus during outputting of said virtual address in said debugging bus cycle; and said trap circuit comprising: virtual address storage means operatively connected to said virtual storage means, said virtual address storage means temporarily storing said virtual address setting means operatively connected to said virtual address storage means, said setting means outputting a set signal for controlling storing of said virtual address into said virtual address storage means on the basis of the first signal and the second signal; trap address storage means operatively connected to said microprocessor, said trap address storage means setting said trap address for trapping said microprocessor; comparing means operatively connected to said virtual address storage means and said trap address storage means, said comparing means comparing the virtual address stored in said virtual address storage means and said trap address stored in said trap address storage means, during the normal bus cycle; and trap demand signal output means operatively connected to said comparing means, said trap demand signal output means outputting a trap demand signal to said microprocessor when said virtual address and said trap address match as a result of said comparing by said comparing means.
Claim 8
Dependent Claim
62 words
A debugging system as set forth in claim 5, which further comprises virtual address selection outputting means operatively connected to said virtual address storage means, said virtual address selection outputting means outputting the virtual address stored in said virtual address storage means to said comparing means on the basis of the first signal and the second signal, during the normal bus cycle.
Claim 9
Dependent Claim
227 words
A debugging system as set forth in claim 5, wherein said virtual address storage means comprises: instruction fetching page number storage means operatively connected to said virtual storage means, said instruction fetching page number storage means storing a first virtual page number for performing an instruction fetch from a plurality of virtual page numbers; data access page storage means operatively connected to said virtual storage means, said data access page storage means storing a second virtual page number for accessing data from the plurality of virtual page numbers, wherein the setting means comprises: trap page number setting means operatively connected to said virtual storage means, said trap page number setting means setting a third virtual page number of said plurality of virtual page numbers wherein said third virtual page number includes said trap address, and trap offset setting means operatively connected to said virtual storage means, said trap offset setting means setting a first offset of the trap address; wherein a fourth virtual page number of said plurality of virtual page numbers includes said virtual address and wherein said comparing means comprises: page number comparing means operatively connected to said virtual storage means, said page number comparing means comparing the fourth virtual page number and the third virtual page number; and offset comparing means for comparing a second offset of said virtual address with the first offset.
Claim 10
Dependent Claim
134 words
A debugging device as set forth in claim 5, wherein said virtual address storage means comprises: instruction fetching page number storage means operatively connected to said virtual storage means, said instruction fetching page number storage means storing a first virtual page number for performing an instruction fetch from a plurality of virtual page numbers; data access page storage means operatively connected to said virtual storage means, said data access page storage means storing a second virtual page number for accessing data from the plurality of virtual page numbers, said setting means storing the first virtual page number in said instruction fetching page number storage means when the first signal indicates instruction fetch and storing the second virtual page number in said data access page number storage means when said first signal indicates data access.
Claim 11
Dependent Claim
30 words
A debugging system as set forth in claim 8, wherein said virtual address selection output means outputs one of the first virtual page number and the second virtual page number.
Claim 12
Dependent Claim
489 words
A debugging system comprising: a microprocessor operatively connected to a data bus and an address bus, said microprocessor including virtual storage means operatively connected to said data bus and said address bus, said virtual storage means providing a virtual storage with a plurality of virtual addresses, said microprocessor for outputting a real address on said address bus during a normal bus cycle and for outputting a virtual address of said plurality of virtual addresses on said address bus during a debugging bus cycle, said microprocessor outputting transfer data and other data signals on said data bus; a memory device connected to said microprocessor through said address bus and said data bus, for storing said transfer data and said other data in memory locations corresponding to said real address and said virtual address; and a bus monitoring device operatively connected to said data bus and said address bus, said bus monitoring device for monitoring, during the debugging bus cycle, said virtual address, said transfer data and said other data signals issued by said microprocessor, said bus monitoring device including a trace circuit operatively connected to said data bus and said address bus, said trace circuit for storing trace data including the virtual address and the transfer data, in order, when said second signal indicates an outputting state of the virtual address from said microprocessor, and said debugging system further including a trap circuit operatively connected to said data bus and said address bus, said trap circuit for outputting a predetermined trap address and a trap demand signal to said microprocessor when said predetermined trap address matches said virtual address during the normal bus cycle, wherein said microprocessor outputs a first signal indicative of a kind of access and a second signal indicative of an outputting state of said virtual address on said data bus during outputting of said virtual address in said debugging bus cycle, and said trace circuit comprises: trace data storage means operatively connected to said data bus and said address bus, said trace data storage means including virtual address storage means operatively connected to said microprocessor, said virtual address storage means storing said trace data; said virtual address storage means temporarily holding said virtual address output in said debugging cycle; setting means operatively connected to said virtual address storage means, said setting means being responsive to said first signal and said second signal, said setting means outputting a set signal to said virtual address storage means for controlling storing of said virtual address in said virtual address storage means; trace address outputting means operatively connected to said trace data storage means, said trace address outputting means generating an address for storing said trace data in said trace data storage means, during said normal bus cycle; and means for outputting an access signal operatively connected to said trace data storage means, said access signal outputting means controlling storage of said trace data into said trace data storage means.
Claim 13
Dependent Claim
489 words
A debugging system comprising: a microprocessor operatively connected to a data bus and an address bus, said microprocessor including virtual storage means operatively connected to said data bus and said address bus, said virtual storage means providing a virtual storage with a plurality of virtual addresses, said microprocessor for outputting a real address on said address bus during a normal bus cycle and for outputting a virtual address of said plurality of virtual addresses on said address bus during a debugging bus cycle, said microprocessor outputting transfer data and other data signals on said data bus; a memory device connected to said microprocessor through said address bus and said data bus, for storing said transfer data and said other data in memory locations corresponding to said real address and said virtual address; and a bus monitoring device operatively connected to said data bus and said address bus, said bus monitoring device for monitoring, during the debugging bus cycle, said virtual address, said transfer data and said other data signals issued by said microprocessor, said bus monitoring device including a trace circuit operatively connected to said data bus and said address bus, said trace circuit for storing trace data including the virtual address and the transfer data, in order, when said second signal indicates an outputting state of the virtual address from said microprocessor, and said debugging system further including a trap circuit operatively connected to said data bus and said address bus, said trap circuit for outputting a predetermined trap address and a trap demand signal to said microprocessor when said predetermined trap address matches said virtual address during the normal bus cycle, wherein said microprocessor outputs a first signal indicative of a kind of access and a second signal indicative of an outputting state of said virtual address on said data bus during outputting of said virtual address in said debugging bus cycle, and said trace circuit comprises: trace data storage means operatively connected to said data bus and said address bus, said trace data storage means including virtual address storage means operatively connected to said microprocessor, said virtual address storage means storing said trace data; said virtual address storage means temporarily holding said virtual address output in said debugging cycle; setting means operatively connected to said virtual address storage means, said setting means being responsive to said first signal and said second signal, said setting means outputting a set signal to said virtual address storage means for controlling storing of said virtual address in said virtual address storage means; trace address outputting means operatively connected to said trace data storage means, said trace address outputting means generating an address for storing said trace data in said trace data storage means, during said normal bus cycle; and means for outputting an access signal operatively connected to said trace data storage means, said access signal outputting means controlling storage of said trace data into said trace data storage means.
Claim 14
Dependent Claim
101 words
A debugging system as set forth in claim 10, wherein said virtual address storage means comprises: instruction fetching page number storage means operatively connected to said virtual storage means, said instruction fetching page number storage means storing a first virtual page number comprising instruction fetching output produced during an instruction fetch from a plurality of virtual page numbers; and data accessing page number storage means operatively connected to said virtual storage means, said data accessing page number storage means storing a second virtual page number comprising data access output produced during access of data among the plurality of virtual page numbers.
Claim 15
Dependent Claim
494 words
A debugging system comprising: a microprocessor operatively connected to a data bus and an address bus, said microprocessor including virtual storage means operatively connected to said data bus and said address bus, said virtual storage means providing a virtual storage with a plurality of virtual addresses, said microprocessor for outputting a real address on said address bus during a normal bus cycle and for outputting a virtual address of said plurality of virtual addresses on said address bus during a debugging bus cycle, said microprocessor outputting transfer data and other data signals on said data bus; a memory device connected to said microprocessor through said address bus and said data bus for storing said transfer data and said other data in memory locations corresponding to said real address and said virtual address; and a bus monitoring device operatively connected to said data bus and said address bus, said bus monitoring device for monitoring, during the debugging bus cycle, said virtual address, said transfer data and said other data signals issued by said microprocessor, said bus monitoring device including a trace circuit operatively connected to said data bus and said address bus said trace circuit for storing trace data including the virtual address and the transfer data, in order, when said second signal indicates an outputting state of the virtual address from said microprocessor, and said debugging system further including a trap circuit operatively connected to said data bus and said address bus, said trap circuit for outputting a predetermined trap address and a trap demand signal to said microprocessor when said predetermined trap address matches said virtual address during the normal bus cycle, wherein said microprocessor outputs a first signal indicative of a kind of access and a second signal indicative of an outputting state of said virtual address on said data bus during outputting of said virtual address in said debugging bus cycle, and said trap circuit comprises: virtual address storage means operatively connected to said virtual storage means, said virtual address storage means temporarily storing said virtual address; setting means operatively connected to said virtual address storage means, said setting means outputting a set signal for controlling storing of said virtual address into said virtual address storage means on the basis of the first signal and the second signal; trap address storage means operatively connected to said microprocessor, said trap address storage means setting said trap address for trapping said microprocessor; comparing means operatively connected to said virtual address storage means and said trap address storage means, said comparing means comparing the virtual address stored in said virtual address storage means and said trap address stored in said trap address storage means, during the normal bus cycle; and trap demand signal output means operatively connected to said comparing means, said trap demand signal output means outputting a trap demand signal to said microprocessor when said virtual address and said trap address match as a result of said comparing by said comparing means.
Claim 16
Dependent Claim
494 words
A debugging system comprising: a microprocessor operatively connected to a data bus and an address bus, said microprocessor including virtual storage means operatively connected to said data bus and said address bus, said virtual storage means providing a virtual storage with a plurality of virtual addresses, said microprocessor for outputting a real address on said address bus during a normal bus cycle and for outputting a virtual address of said plurality of virtual addresses on said address bus during a debugging bus cycle, said microprocessor outputting transfer data and other data signals on said data bus; a memory device connected to said microprocessor through said address bus and said data bus for storing said transfer data and said other data in memory locations corresponding to said real address and said virtual address; and a bus monitoring device operatively connected to said data bus and said address bus, said bus monitoring device for monitoring, during the debugging bus cycle, said virtual address, said transfer data and said other data signals issued by said microprocessor, said bus monitoring device including a trace circuit operatively connected to said data bus and said address bus said trace circuit for storing trace data including the virtual address and the transfer data, in order, when said second signal indicates an outputting state of the virtual address from said microprocessor, and said debugging system further including a trap circuit operatively connected to said data bus and said address bus, said trap circuit for outputting a predetermined trap address and a trap demand signal to said microprocessor when said predetermined trap address matches said virtual address during the normal bus cycle, wherein said microprocessor outputs a first signal indicative of a kind of access and a second signal indicative of an outputting state of said virtual address on said data bus during outputting of said virtual address in said debugging bus cycle, and said trap circuit comprises: virtual address storage means operatively connected to said virtual storage means, said virtual address storage means temporarily storing said virtual address; setting means operatively connected to said virtual address storage means, said setting means outputting a set signal for controlling storing of said virtual address into said virtual address storage means on the basis of the first signal and the second signal; trap address storage means operatively connected to said microprocessor, said trap address storage means setting said trap address for trapping said microprocessor; comparing means operatively connected to said virtual address storage means and said trap address storage means, said comparing means comparing the virtual address stored in said virtual address storage means and said trap address stored in said trap address storage means, during the normal bus cycle; and trap demand signal output means operatively connected to said comparing means, said trap demand signal output means outputting a trap demand signal to said microprocessor when said virtual address and said trap address match as a result of said comparing by said comparing means.
Claim 17
Dependent Claim
227 words
A debugging system as set forth in claim 12, wherein said virtual address storage means comprises: instruction fetching page number storage means operatively connected to said virtual storage means, said instruction fetching page number storage means storing a first virtual page number for performing an instruction fetch from a plurality of virtual page numbers; data access page storage means operatively connected to said virtual storage means, said data access page storage means storing a second virtual page number for accessing data from the plurality of virtual page numbers, wherein the setting means comprises: trap page number setting means operatively connected to said virtual storage means, said trap page number setting means setting a third virtual page number of said plurality of virtual page numbers wherein said third virtual page number includes said trap address, and trap offset setting means operatively connected to said virtual storage means, said trap offset setting means setting a first offset of the trap address; wherein a fourth virtual page number of said plurality of virtual page numbers includes said virtual address and wherein said comparing means comprises: page number comparing means operatively connected to said virtual storage means, said page number comparing means comparing the fourth virtual page number and the third virtual page number; and offset comparing means for comparing a second offset of said virtual address with the first offset.
Claim 18
Dependent Claim
134 words
A debugging system as set forth in claim 15, wherein said virtual address storage means comprises: instruction fetching page number storage means operatively connected to said virtual storage means, said instruction fetching page number storage means storing a first virtual page number for performing an instruction fetch from a plurality of virtual page numbers; data access page storage means operatively connected to said virtual storage means, said data access page storage means storing a second virtual page number for accessing data from the plurality of virtual page numbers, said setting means storing the first virtual page number in said instruction fetching page number storage means when the first signal indicates instruction fetch and storing the second virtual page number in said data access page number storage means when said first signal indicates data access.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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