US4965720A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Directed address generation for virtual-address data processors
Assignee: International Business Machines Corp
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Filing: 1989-08-08
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Granted: 1990-10-23
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Expires: 2009-08-08
Abstract
Abstract In a processor having a real address space larger than its virtual address space, all of the physical memory is addressed by using a separate prefix register associated with each of the address registers to hold both a high-order address portion and a control bit specifying whether the address is to be translated or used as a direct real address.
Inventors
- 👤 Glen R. Mitchell
- 👤 Richard G. Mustain
- 👤 Jon H. Peterson
- 👤 Lawrence D. Whitley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 15:24
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/0223; G06F12/0292
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
186 words
In a data processor, the combination comprising: a memory having an address input for receiving a real address in a real address space; a common bus for transferring data to and from a plurality of registers; address-register means coupled to said common bus for holding a virtual address capable of addressing a virtual address space substantially smaller than said real address space, said virtual address having a segment portion and an offset portion; a set of address-translation registers for converting said segment portion into a page portion of a real address, said page portion being substantially larger than said segment portion; prefix-address register means coupled to said common bus for holding a partial direct-address specification having a control portion and a block portion; switching means responsive to said prefix-address control portion for selectively coupling to a switching-means output either said address-translation registers or said prefix-address block portions along with a portion of said address-register means; means for coupling to said address input a set of low-order bits comprising said offset portion of said register-address means catenated with a set of high-order bits comprising said switching-means output.
Claim 2
Dependent Claim
186 words
In a data processor, the combination comprising: a memory having an address input for receiving a real address in a real address space; a common bus for transferring data to and from a plurality of registers; address-register means coupled to said common bus for holding a virtual address capable of addressing a virtual address space substantially smaller than said real address space, said virtual address having a segment portion and an offset portion; a set of address-translation registers for converting said segment portion into a page portion of a real address, said page portion being substantially larger than said segment portion; prefix-address register means coupled to said common bus for holding a partial direct-address specification having a control portion and a block portion; switching means responsive to said prefix-address control portion for selectively coupling to a switching-means output either said address-translation registers or said prefix-address block portions along with a portion of said address-register means; means for coupling to said address input a set of low-order bits comprising said offset portion of said register-address means catenated with a set of high-order bits comprising said switching-means output.
Claim 3
Dependent Claim
54 words
The combination of claim 1, wherein said address-register means comprises a bank of individual address registers, wherein said prefix-register means comprises a bank of individual prefix registers, and wherein said processor further includes control means for selecting corresponding ones of said address and prefix registers to provide said offset, segment, block, and control portions.
Claim 4
Dependent Claim
30 words
The combination of claim 1, wherein said switching means is further responsive to said prefix-address control portion to couple said segment portion of said virtual-address register to said switching-means output.
Claim 5
Dependent Claim
37 words
The combination of claim 3, wherein said switching means is responsive to said prefix-address register control portion to form said real address from said prefix-address register block portion, said address-register segment portion, and said address-register offset portion.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-22 | 1994-04-23 | 1994-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-22 | 1998-04-23 | 1998-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-22 | 2002-04-23 | 2002-10-23 | $7700.00 | Window Closed / Lapsed |