Address translation with storage protection

Claim 2

In a computer system including an addressable selectively operable storage, a central processing unit and I/O devices the improvement comprising an addressable register, a source of storage addresses for addressing storage and a special address distinguishable from said storage addresses for storage protection, means for selectively loading said addressable register with a storage address from said source of storage addresses when said loaded storage address is to address an unprotected storage location or with said special address for storage protection, means for generating an address translate control signal, addressing means for addressing said storage and for selectively addressing said addressable register, means selectively connectable under control of said address translate control signal to said addressable register for passing a storage address to said storage when said addressable register upon being addressed contains a storage address, means selectively connectable to said addressable register under control of said address translate control signal for generating a storage inhibit signal when said addressable register upon being addressed by said addressing means contains said special address instead of a storage address, and means for applying said storage inhibit signal to said storage.

Claim 3

The computer system of claim 1 further comprising first means operably controlled by said central processing unit during task operations for controlling selective operation of said addressing means to enable or disable addressing of said addressable register.

Claim 4

The computer system of claim 1 further comprising second means operably controlled by said central processing unit during I/O operations for controlling selective operation of said addressing means to enable or disable addressing of said addressable register.

Claim 5

The computer system of claim 1 wherein said special address consists of bits having a one state.

Claim 6

The computer system of claim 1 further comprising a second addressable register connected to be addressed by said addressing means and to be loaded with a storage address from said source of storage addresses or with said special address by said means for selectively loading said addressable register and selectively connectable under control of said address translate control signal to said means for generating said storage inhibit signal, and control means connected to control selective connection of said means for generating said storage inhibit signal when said addressable or second addressable registers are addressed by said addressing means.

Claim 7

The computer system of claim 5 wherein the selection made by said control means is determined by said central processing unit.

Claim 8

The computer system of claim 6 wherein said control means is caused by said central processing unit to select said addressable register for task operations and to select said second addressable register for I/O operations.

Claim 9

In a computer system having an addressable selectively operable storage, a storage address register, a source of storage addresses, means for loading storage addresses from said source of storage addresses into said storage address register the improvement comprising an addressable set of task translation registers, an addressable set of I/O translation registers, means for loading said task and I/O translation registers with first or second types of addresses, said first type of address being a translated address and said second type of address being a storage protection address, reading means for selectively reading addresses from said task and I/O translation registers, means responsive to said first addresses being read from said task or from said I/O translation registers for concatenating said read first addresses with the address from said address register to form an address for addressing storage, and means responsive to said second addresses being read from said task or from said I/O translation registers for inhibiting storage addressing.

Claim 10

In a computer system having an addressable selectively operable storage, a storage address register, a source of storage addresses, means for loading storage addresses from said source of storage addresses into said storage address register the improvement comprising an addressable set of task translation registers, an addressable set of I/O translation registers, means for loading said task and I/O translation registers with first or second types of addresses, said first type of address being a translated address and said second type of address being a storage protection address, reading means for selectively reading addresses from said task and I/O translation registers, means responsive to said first addresses being read from said task or from said I/O translation registers for concatenating said read first addresses with the address from said address register to form an address for addressing storage, and means responsive to said second addresses being read from said task or from said I/O translation registers for inhibiting storage addressing.

Claim 11

In a computer system having an addressable selectively operable main storage containing main storage instructions and data, a first central processing unit connected to execute main storage instructions fetched from main storage, an addressable control storage containing control instructions, a second central processing unit connected to execute control instructions fetched from said control storage and connected to transfer data to and from said main storage, I/O devices connected for operation under control of said second central processing unit, the improvement comprising: a main storage address register, a source of main storage addresses, means for loading said main storage address register with addresses from said source of main storage addresses, a program mode register containing bit states for controlling main storage addressing intranslate and nontranslate modes, a control mode register containing bit states for controlling main storage addressing in translate and nontranslate modes, first means connected under control of said first central processing unit to said program mode register and responsive to bit states in said program mode register for selectively generating translate signals, second means connected under control of said second central processing unit to said control mode register and responsive to bit states in said control mode register for selectively generating translate signals, an addressable set of task translation registers connected for addressing under control of said main storage address register, said task translation registers being loaded with first or second types of addresses, said first type of address being a translated address and said second type of address being a storage protection address, an addressable set of I/O translation registers connected for addressing under control of said main storage address register, said I/O translation registers being loaded with said first or second types of addresses, main storage address decode means connected to receive addresses from said main storage address register and from said task or I/O translation registers depending upon whether a task or an I/O operation is in progress and for generating a main storage address from the address in said main storage address register in the absence of a translate signal from said first and second means or from the address in said main storage address register together with first types of addresses from said task translation registers for task operations or from said I/O translation registers for I/O operations in the presence of a translate signal from said first or second means, means responsive to second types of addresses from said task translation registers during task operations or from said I/O translation registers during I/O operations for generating main storage addressing inhibit signals, and means for applying said main storage addressing inhibit signals to said main storage address decode means to inhibit the addressing of said main storage.

Claim 12

In a computer system having an addressable selectively operable main storage containing main storage instructions and data, a first central processing unit connected to execute main storage instructions fetched from main storage, an addressable control storage containing control instructions, a second central processing unit connected to execute control instructions fetched from said control storage and connected to transfer data to and from said main storage, I/O devices connected for operation under control of said second central processing unit, the improvement comprising: a main storage address register, a source of main storage addresses, means for loading said main storage address register with addresses from said source of main storage addresses, a program mode register containing bit states for controlling main storage addressing intranslate and nontranslate modes, a control mode register containing bit states for controlling main storage addressing in translate and nontranslate modes, first means connected under control of said first central processing unit to said program mode register and responsive to bit states in said program mode register for selectively generating translate signals, second means connected under control of said second central processing unit to said control mode register and responsive to bit states in said control mode register for selectively generating translate signals, an addressable set of task translation registers connected for addressing under control of said main storage address register, said task translation registers being loaded with first or second types of addresses, said first type of address being a translated address and said second type of address being a storage protection address, an addressable set of I/O translation registers connected for addressing under control of said main storage address register, said I/O translation registers being loaded with said first or second types of addresses, main storage address decode means connected to receive addresses from said main storage address register and from said task or I/O translation registers depending upon whether a task or an I/O operation is in progress and for generating a main storage address from the address in said main storage address register in the absence of a translate signal from said first and second means or from the address in said main storage address register together with first types of addresses from said task translation registers for task operations or from said I/O translation registers for I/O operations in the presence of a translate signal from said first or second means, means responsive to second types of addresses from said task translation registers during task operations or from said I/O translation registers during I/O operations for generating main storage addressing inhibit signals, and means for applying said main storage addressing inhibit signals to said main storage address decode means to inhibit the addressing of said main storage.

Claim 13

The computer system of claim 9 wherein said I/O devices are connected to operate under control of said second central processing unit on interrupt levels and further comprising third means for generating translate signals in response to certain of said interrupt levels being active.

Claim 14

The computer system of claim 9 wherein the bits states of said program mode register and said control mode register are settable under control of said second central processing unit.

Claim 15

In a computer system including main storage with addressable location containing data and a central processing unit for retrieving data from, and storing data into, said addressable locations, the improvement comprising: a source of storage addresses, a storage address register, means for loading addresses from said source of storage addresses into said storage address register, a source of translated addresses, a special address distinguishable from any of said translated addresses, an address translate register addressable by said storage address register, means for selectively loading said address translate register with one of said translated addresses for storage addressing or with said special address for storage protection, address translate control means for selectively providing an address translate control signal, storage protect means connected to said address translate register, and operative in response to receiving said address translate control signal for generating an inhibit storage signal when said address translate register contains said special address, address decode means responsive to said address translate control signal and the absence of said inhibit storage signal for providing a discrete address to said storage by decoding an address from said storage address register and from said address translate register, means for applying said address translate control signal to said storage protect and said address decode means, and means for applying said inhibit storage signal to said address decode means.

Claim 16

In a computer system including main storage with addressable location containing data and a central processing unit for retrieving data from, and storing data into, said addressable locations, the improvement comprising: a source of storage addresses, a storage address register, means for loading addresses from said source of storage addresses into said storage address register, a source of translated addresses, a special address distinguishable from any of said translated addresses, an address translate register addressable by said storage address register, means for selectively loading said address translate register with one of said translated addresses for storage addressing or with said special address for storage protection, address translate control means for selectively providing an address translate control signal, storage protect means connected to said address translate register, and operative in response to receiving said address translate control signal for generating an inhibit storage signal when said address translate register contains said special address, address decode means responsive to said address translate control signal and the absence of said inhibit storage signal for providing a discrete address to said storage by decoding an address from said storage address register and from said address translate register, means for applying said address translate control signal to said storage protect and said address decode means, and means for applying said inhibit storage signal to said address decode means.