US3839706A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Input/output channel relocation storage protect mechanism
Assignee: International Business Machines Corp
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Filing: 1973-07-02
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Granted: 1974-10-01
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Expires: 1993-07-02
Abstract
Abstract An input/output data channel operates in conjunction with a virtual memory computer. A channel operation is commenced with the execution of a start I/O instruction which transfers a channel address word (CAW) to the channel. The CAW contains a virtual command address pointing to the beginning of a virtual channel program. The virtual command address is presented to a channel look-aside buffer which translates the virtual command to a real memory address for accessing main storage. The virtual channel command words (CCW''s) which comprise the channel program are successively translated by the channel look-aside buffer. A virtual address stack within the buffer holds active virtual data addresses and command addresses for each channel. Interlocking between this stack and a CPU translation mechanism is provided by an I/O bit array. The I/O bit array contains a count mechanism for each memory frame which may be addressed by the channel. Each time a memory frame is addressed by any of the channels, the corresponding count is incremented. Similarly, when any of the channels are through with the memory frame, the count is decremented. Thus, so long as there is an outstanding access to the memory frame, there is a non-zero count in the corresponding count position. The non-zero condition is transmitted to a CPU storage protect area to insure that the CPU does not try to use the same memory frame that the channel is accessing.
Inventors
- 👤 E Borchsenius
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 01:03
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/52; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F13/00; G06F13/10; G06F12/1081
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
106 words
An input/output data channel for use with a virtual memory computer including a CPU and a memory divided into memory frames comprising: means for fetching a control word containing a virtual command address referring to a channel program; means for translating the virtual command address in said control word to a real memory address for accessing said virtual memory; means for storing said virtual and real addresses; and registering means responsive to said real addresses for storing an indication that the real memory frame corresponding to said real memory address is being used by said channel to prevent the CPU from accessing the same memory frame.
Claim 2
Dependent Claim
106 words
An input/output data channel for use with a virtual memory computer including a CPU and a memory divided into memory frames comprising: means for fetching a control word containing a virtual command address referring to a channel program; means for translating the virtual command address in said control word to a real memory address for accessing said virtual memory; means for storing said virtual and real addresses; and registering means responsive to said real addresses for storing an indication that the real memory frame corresponding to said real memory address is being used by said channel to prevent the CPU from accessing the same memory frame.
Claim 3
Dependent Claim
59 words
The combination according to claim 1 inclUding further means for fetching a control word stored at said real address, said control word containing a virtual data address referring to a memory location to or from which data are to be transferred, and means for translating the virtual data address to a real data address for accessing said memory location.
Claim 4
Dependent Claim
59 words
The combination according to claim 1 wherein said registering means includes an I/O bit array containing a count mechanism for each memory frame which may be addressed by a channel and means operative each time a particular memory frame is addressed by any one of a plurality of channels for incrementing the count corresponding to said particular memory frame.
Claim 5
Dependent Claim
20 words
The combination according to claim 3 including means operative at the end of a channel operation for decrementing said count.
Claim 6
Dependent Claim
127 words
An input/output data channel for use with a virtual memory computer including a CPU comprising: means for fetching a channel address word (CAW) containing a virtual command address referring to the beginning of a channel program; means for translating the virtual command address in said CAW to a real memory address for accessing said virtual memory; means for translating virtual data addresses and command address contained in said channel program to real addresses for accessing said virtual memory; means for storing said virtual and real addresses; and registering means responsive to said real addresses for storing on indication that the real memory frame corresponding to said real memory address is being used by said channel to thereby prevent the CPU from paging out the same memory frame.
Claim 7
Dependent Claim
127 words
An input/output data channel for use with a virtual memory computer including a CPU comprising: means for fetching a channel address word (CAW) containing a virtual command address referring to the beginning of a channel program; means for translating the virtual command address in said CAW to a real memory address for accessing said virtual memory; means for translating virtual data addresses and command address contained in said channel program to real addresses for accessing said virtual memory; means for storing said virtual and real addresses; and registering means responsive to said real addresses for storing on indication that the real memory frame corresponding to said real memory address is being used by said channel to thereby prevent the CPU from paging out the same memory frame.
Claim 8
Dependent Claim
59 words
The combination according to claim 5 wherein said registering means includes an I/O bit array containing a count mechanism for each memory frame which may be addressed by a channel and means operative each time a particular memory frame is addressed by any one of a plurality of channels for incrementing the count corresponding to said particular memory frame.
Claim 9
Dependent Claim
20 words
The combination according to claim 6 including means operative at the end of a channel operation for decrementing said count.
Claim 10
Dependent Claim
175 words
In an input/output data channel for use with a virtual memory computer wherein a channel operation is commenced with the execution of an instruction which initiates a virtual channel program comprised of a sequence of control words containing virtual command or data addresses, means for translating said virtual channel program to real and for interlocking the operation of said channel with said computer, comprising: means responsive to said instruction for transferring to said channel control information for referencing translation tables; buffer storage means including means for holding active virtual data addresses and command addresses for said channel; said buffer storage means also provided with means for storing said control information in conjunction with real data and real command address; means operative in cooperation with said buffer storage means and said control information for translating virtual addresses to real addresses; and means for storing said virtual and real addresses in said buffer storage means, whereby as virtual addresses are translated during the execution of said channel program the real addresses are stored with the virtual addresses.
Claim 11
Dependent Claim
175 words
In an input/output data channel for use with a virtual memory computer wherein a channel operation is commenced with the execution of an instruction which initiates a virtual channel program comprised of a sequence of control words containing virtual command or data addresses, means for translating said virtual channel program to real and for interlocking the operation of said channel with said computer, comprising: means responsive to said instruction for transferring to said channel control information for referencing translation tables; buffer storage means including means for holding active virtual data addresses and command addresses for said channel; said buffer storage means also provided with means for storing said control information in conjunction with real data and real command address; means operative in cooperation with said buffer storage means and said control information for translating virtual addresses to real addresses; and means for storing said virtual and real addresses in said buffer storage means, whereby as virtual addresses are translated during the execution of said channel program the real addresses are stored with the virtual addresses.
Claim 12
Dependent Claim
195 words
The combination according to claim 8 further comprising: means operative in conjunction with said buffer storage means for fetching command and data addresses in accordance with said real addresses translated from said control words; means for incrementing a fetched data address to point to the next successive data address; registering means responsive to said real addresses for storing indications of I/O references to said memory including a count mechanism for each frame which may be addressed by each of a plurality of channels similar to said channel, wherein upon each reference to a memory frame the corresponding count is incRemented and wherein said count is decremented by said channel when it releases said frame from use, whereby so long as there is an outstanding access to said memory frame, there is a non-zero count in the corresponding count position; means responsive to said registering means for generating an I/O summary bit which indicates the non-zero condition of an addressed memory frame count; and means for transmitting said bit to a storage protect area whereby interlocking is provided between memory users to prevent the other users from accessing the memory frame that said channel is using.
Claim 13
Dependent Claim
231 words
In an input/output data channel for use with a virtual memory computer operating with a paging supervisor wherein a channel operation is commenced with the execution of a start I/O instruction which transfers a channel address word (CAW) from a real area in memory to the channel, said CAW containing a virtual command address pointing to the beginning of a virtual channel program comprised of a sequence of channel command words (CCW''s) containing virtual command or data addresses, means for translating said virtual channel program to real and for interlocking the operation of said channel with said computer, comprising: means responsive to said start I/O instruction for transferring from an I/O control area to said channel a segment table origin word (STO) and translation control bits (TCR), said means including means for energizing a relocate mode bit in said CAW; a channel look-aside buffer containing a virtual address stack for holding active virtual data address and command addresses for said channel; said channel look-aside buffer provided with means for storing said STO, TCR, and relocate mode bits; and means operative in cooperation with said channel look-aside buffer for translating virtual addresses to real addresses, said means including means for storing said virtual addresses in said virtual address stack, whereby as virtual addresses are translated during the execution of said channel program the virtual addresses are stored in said virtual address stack.
Claim 14
Dependent Claim
231 words
In an input/output data channel for use with a virtual memory computer operating with a paging supervisor wherein a channel operation is commenced with the execution of a start I/O instruction which transfers a channel address word (CAW) from a real area in memory to the channel, said CAW containing a virtual command address pointing to the beginning of a virtual channel program comprised of a sequence of channel command words (CCW''s) containing virtual command or data addresses, means for translating said virtual channel program to real and for interlocking the operation of said channel with said computer, comprising: means responsive to said start I/O instruction for transferring from an I/O control area to said channel a segment table origin word (STO) and translation control bits (TCR), said means including means for energizing a relocate mode bit in said CAW; a channel look-aside buffer containing a virtual address stack for holding active virtual data address and command addresses for said channel; said channel look-aside buffer provided with means for storing said STO, TCR, and relocate mode bits; and means operative in cooperation with said channel look-aside buffer for translating virtual addresses to real addresses, said means including means for storing said virtual addresses in said virtual address stack, whereby as virtual addresses are translated during the execution of said channel program the virtual addresses are stored in said virtual address stack.
Claim 15
Dependent Claim
214 words
The combination according to claim 10, further comprising: means operative in conjunction with said channel look-aside buffer for fetching command and data addresses in accordance with addresses provided by said CAW and said channel command words, said means including means for sequentially incrementing said data addresses to point to successive data addresses; means for fetching successive memory frames at locations specified by said successive data addresses; registering means responsive to said real addresses for storing indications of I/O references to said memory including a count mechanism for each frame which may be addressed by each of a plurality of channels similar to said channel, wherein upon each reference to a memory frame the corresponding count is incremented and wherein said count is decremented by said channel when it releases said frame from use, whereby so long as there is an outstanding access to said memory frame, there is a non-zero count in the corresponding count position; means responsive to said interlocking means for generating an I/O summary bit which indicates the non-zero condition of an addressed memory frame; and means for transmitting said I/O summary bit to a storage protect area whereby interlocking is provided between memory users to prevent the other users from paging out said memory frame that said channel is using.
Claim 16
Dependent Claim
64 words
The combination according to claim 10 wherein said channel includes means for creating a channel status word (CSW) and, means in said CSW for indicating by a predetermined selectable state, that a paging fault has occurred, means for transferring to a control area a page fault address, and means for turning on a page fault indicator, whereby interfacing with said paging supervisor is provided.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-09-30 | 1978-04-01 | 1978-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-09-30 | 1982-04-01 | 1982-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-09-30 | 1986-04-01 | 1986-10-01 | $7700.00 | Window Closed / Lapsed |