US4602329A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processing system having an address translation unit shared by a CPU and a channel unit
Assignee: NEC Corp
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Filing: 1984-03-23
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Granted: 1986-07-22
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Expires: 2004-03-23
Abstract
Abstract In a data processing system for use in accessing a main memory from each of a central processing unit and a channel unit through a common data bus, an address translation circuit is incorporated in the central processing unit so as to translate each logical address into a real address physically allotted to the main memory and is used in common by the central processing unit and the channel unit. Address translation is carried out by the address translation circuit selectively for the central processing unit and the channel unit. When the main memory is accessed from the channel unit through the central processing unit, an indication signal is delivered from the main memory only to the central processing unit to indicate either reception or supply of a data group. The central processing unit energizes the channel unit to assign the data bus to the channel unit. Thereafter, the data group is transferred between the main memory and the channel unit through the data bus.
Inventors
- 👤 Akihito Ohtake
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:47
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/0223; G06F12/0292; G06F12/08; G06F12/10; G06F12/1081
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
253 words
In a data processing system for use in accessing a main memory from each of a central processing unit and a channel unit through a data bus shared by said central processing and said channel units, said central processing unit comprising first access signal producing means for producing a first access signal and first request signal producing means for producing a first request signal, and channel unit comprising second access signal producing means for producing a second access signal and second request signal producing means for producing a second access signal, said main memory producing an acknowledgement signal when accessed, the improvement wherein said central processing unit further comprises: first delivering means responsive to a selected one of said first and second access signals for delivering a third access signal to said main memory through said data bus; second delivering means operatively coupled to said first delivering means for delivering one of said first and said second request signals to said main memory that is selected in correspondence to said selected one of said first and said second access signals; and energizing means operatively coupled to said second delivering means and at least to said second request signal producing means and responsive to said acknowledgement signal for energizing said channel unit with said data bus assigned to said channel unit when said second request signal producing means produces said second request signal and said second delivering means delivers said second request signal as said one of the first and the second request signals.
Claim 2
Dependent Claim
253 words
In a data processing system for use in accessing a main memory from each of a central processing unit and a channel unit through a data bus shared by said central processing and said channel units, said central processing unit comprising first access signal producing means for producing a first access signal and first request signal producing means for producing a first request signal, and channel unit comprising second access signal producing means for producing a second access signal and second request signal producing means for producing a second access signal, said main memory producing an acknowledgement signal when accessed, the improvement wherein said central processing unit further comprises: first delivering means responsive to a selected one of said first and second access signals for delivering a third access signal to said main memory through said data bus; second delivering means operatively coupled to said first delivering means for delivering one of said first and said second request signals to said main memory that is selected in correspondence to said selected one of said first and said second access signals; and energizing means operatively coupled to said second delivering means and at least to said second request signal producing means and responsive to said acknowledgement signal for energizing said channel unit with said data bus assigned to said channel unit when said second request signal producing means produces said second request signal and said second delivering means delivers said second request signal as said one of the first and the second request signals.
Claim 3
Dependent Claim
75 words
A data processing system as claimed in claim 1, said first and said second access signals comprising first and second address signals given in the form of logical addresses, respectively, said third access signal comprising a third address signal for physically specifying each address of said main memory, wherein said first delivering means comprising: address converting means for converting a selected one of said first and said second address signals into said third address signal.
Claim 4
Dependent Claim
73 words
A data processing system as claimed in claim 2, said first and said second access signals comprising first and second command signals related to said first and second address signals to specify commands to be sent to said main memory, respectively, wherein said first delivering means comprises: means for supplying said main memory with a selected one of said first and said second command signals as a part of said third access signal.
Claim 5
Dependent Claim
101 words
A data processing system as claimed in claim 1, wherein said energizing means comprises: means responsive to said request acknowledgement signal and coupled to said first and said second request producing means for supplying said channel unit with a channel energization signal so as to allot said data bus to said channel unit when said second request signal is sent to said main memory as said selected request signal; said channel unit comprising: means operatively coupled to said second access signal producing means and responsive to said channel energization signal for carrying out operation in accordance with said second access signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-07-21 | 1990-01-20 | 1990-07-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-07-21 | 1994-01-20 | 1994-07-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-07-21 | 1998-01-20 | 1998-07-22 | $7700.00 | Window Closed / Lapsed |