Volatile memory cell with interface charge traps

Claim 2

A volatile memory cell comprising an insulated gate field effect transistor with charge traps in an insulating layer, wherein substantially all of said charge traps are located within approximately 1.0 nm of an interface between a semiconductor layer and the insulating layer.

Claim 3

The volatile memory cell of claim 1, wherein substantially all of said charge traps are located within approximately 0.5-0.7 nm of the interface.

Claim 4

The volatile memory cell of claim 1, wherein the semiconductor layer comprises P-type doped silicon and the insulating layer comprises a layer of silicon dioxide containing implanted silicon ions forming said charge traps.

Claim 5

The volatile memory cell of claim 1 wherein the semiconductor layer comprises Indium Phosphide and the insulating layer comprises Silicon Nitride.

Claim 6

A volatile memory device comprising a plurality of memory cells according to claim 1, arranged in rows and columns to allow addressing of individual cells by control circuitry connected to said volatile memory device.

Claim 7

The volatile memory cell of claim 1, wherein: a trap energy level of the charge traps has a value close to an edge of a silicon conduction band.

Claim 8

A semiconductor device comprising: a semiconductor layer; an insulating layer disposed on the semiconductor layer defining an interface between the semiconductor layer and the insulating layer; charge traps located in the insulating layer, said charge traps for retaining charge; wherein substantially all of the charge traps are located within approximately 1.0 nm from the interface.

Claim 9

A semiconductor device comprising: a semiconductor layer; an insulating layer disposed on the semiconductor layer defining an interface between the semiconductor layer and the insulating layer; charge traps located in the insulating layer, said charge traps for retaining charge; wherein substantially all of the charge traps are located within approximately 1.0 nm from the interface.

Claim 10

A memory device comprising: a semiconductor layer; an insulating layer disposed on the semiconductor layer defining an interface between the semiconductor layer and the insulating layer; charge traps located in the insulating layer; wherein substantially all of said charge traps are located within 1.0 nm of the interface.

Claim 11

A memory device comprising: a semiconductor layer; an insulating layer disposed on the semiconductor layer defining an interface between the semiconductor layer and the insulating layer; charge traps located in the insulating layer; wherein substantially all of said charge traps are located within 1.0 nm of the interface.

Claim 12

The semiconductor device of claim 7, wherein substantially all of the charge traps are located within, approximately 0.5-0.7 nm of the interface.

Claim 13

A memory device comprising: an insulated gate field effect transistor including an insulating layer having a common interface with a semiconductor substrate, charge traps located in the insulating layer, said charge traps for retaining charge, wherein substantially all of said charge traps are located within approximately 1.0 nm of said common interface, and wherein said retained charge modulates a threshold of the transistor.

Claim 14

A memory device comprising: an insulated gate field effect transistor including an insulating layer having a common interface with a semiconductor substrate, charge traps located in the insulating layer, said charge traps for retaining charge, wherein substantially all of said charge traps are located within approximately 1.0 nm of said common interface, and wherein said retained charge modulates a threshold of the transistor.

Claim 15

The memory device of claim 10, wherein substantially all of the charge traps are located within approximately 0.5-0.7 nm of the interface.

Claim 16

A memory device comprising: an insulated gate field effect transistor including an insulating layer disposed on a semiconductor substrate; charge traps located in the insulating layer, said charge traps for retaining charge for a finite period of time; said retained charge modulating a threshold of the transistor; wherein substantially all of the charge traps are located within approximately 1.0 nm of an interface between the insulating layer and the substrate; and wherein the finite period of time is a function of a density of the charge traps in the insulating layer and the distance to the interface.

Claim 17

A memory device comprising: an insulated gate field effect transistor including an insulating layer disposed on a semiconductor substrate; charge traps located in the insulating layer, said charge traps for retaining charge for a finite period of time; said retained charge modulating a threshold of the transistor; wherein substantially all of the charge traps are located within approximately 1.0 nm of an interface between the insulating layer and the substrate; and wherein the finite period of time is a function of a density of the charge traps in the insulating layer and the distance to the interface.

Claim 18

A memory circuit comprising: a control circuit for reading and writing to individual memory cells; and a plurality of memory cells arranged in rows and columns to allow addressing of individual cells by the control circuit; each of said memory cells comprising an insulated gate field effect transistor with charge traps in an insulating layer, wherein substantially all of the charge traps are located within approximately 1.0 nm of an interface between a semiconductor layer and the insulating layer; and wherein, for each transistor, a gate is connected to a wordline, a source is connected to a first bit-line and a drain is connected to a second bit-line.

Claim 19

A memory circuit comprising: a control circuit for reading and writing to individual memory cells; and a plurality of memory cells arranged in rows and columns to allow addressing of individual cells by the control circuit; each of said memory cells comprising an insulated gate field effect transistor with charge traps in an insulating layer, wherein substantially all of the charge traps are located within approximately 1.0 nm of an interface between a semiconductor layer and the insulating layer; and wherein, for each transistor, a gate is connected to a wordline, a source is connected to a first bit-line and a drain is connected to a second bit-line.

Claim 20

The memory circuit of claim 13, wherein substantially all of the charge traps are located within approximately 0.5-0.7 nm of the interface.

Claim 21

The memory circuit comprising: a control circuit for reading and writing to individual memory cells; and a plurality of memory cells arranged in rows and columns to allow addressing of individual cells by the control circuit, each of said memory cells comprising an insulated gate field effect transistor with charge traps in an insulating layer, said charge traps for retaining charge at or near an interface between a semiconductor layer and the insulating layer, said retained charge for modulating a threshold of the transistor; wherein substantially all of the change traps are located within approximately 1.0 nm of the interface; and wherein, for each transistor, a gate is connected to a wordline, a source is connected to a first bit-line and a drain is connected to a second bit-line.

Claim 22

The memory circuit comprising: a control circuit for reading and writing to individual memory cells; and a plurality of memory cells arranged in rows and columns to allow addressing of individual cells by the control circuit, each of said memory cells comprising an insulated gate field effect transistor with charge traps in an insulating layer, said charge traps for retaining charge at or near an interface between a semiconductor layer and the insulating layer, said retained charge for modulating a threshold of the transistor; wherein substantially all of the change traps are located within approximately 1.0 nm of the interface; and wherein, for each transistor, a gate is connected to a wordline, a source is connected to a first bit-line and a drain is connected to a second bit-line.

Claim 23

The memory circuit of claim 15, wherein substantially all the charge traps are located within approximately 0.5-0.7 nm of the interface.