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US5607871A
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Method of manufacturing a flash EEPROM cell using the select gates as a mask
Assignee: SK Hynix Inc
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Filing: 1996-02-05
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Granted: 1997-03-04
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Expires: 2016-02-05
Abstract
Abstract A method of manufacturing a flash EEPROM cell with a split-gate structure which can improve the electrical characteristics of the cell by forming a source region through an ion implantation method using a select gate as a mask to prevent the reduction in the electrical characteristics of a gate oxide layer is disclosed.
Inventors
- 👤 Sung O. Han
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:36
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10P; H10P14/00; H10P14/40; H10P14/416; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/6922; H10P14/6923; H10P50/00; H10P50/71; H10P76/00; H10P76/20; H10P76/204; H10P76/2041
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
171 words
A method of manufacturing a flash EEPROM cell, comprising the steps of: sequentially forming a tunnel oxide layer, a floating gate, a dielectric layer, a program gate and an insulating layer on a silicon substrate, thereby forming a gate electrode; forming a drain region in said silicon substrate of a side of said gate electrode; forming a side wall insulating layer on the side wall of said gate electrode; forming a select gate oxide layer on an exposed portion of said silicon substrate; forming a polysilicon layer on the resulting structure after forming said select gate oxide layer; patterning said polysilicon layer so that a portion of said select gate oxide layer is exposed, thereby forming a select gate; forming a source region in a selected portion of said silicon substrate; sequentially depositing an oxide layer and a BPSG layer after forming said source region; exposing a portion of said select gate, thereby forming a contact hole; and forming a word line on the resulting structure after forming said contact hole.
Claim 2
Independent Claim
171 words
A method of manufacturing a flash EEPROM cell, comprising the steps of: sequentially forming a tunnel oxide layer, a floating gate, a dielectric layer, a program gate and an insulating layer on a silicon substrate, thereby forming a gate electrode; forming a drain region in said silicon substrate of a side of said gate electrode; forming a side wall insulating layer on the side wall of said gate electrode; forming a select gate oxide layer on an exposed portion of said silicon substrate; forming a polysilicon layer on the resulting structure after forming said select gate oxide layer; patterning said polysilicon layer so that a portion of said select gate oxide layer is exposed, thereby forming a select gate; forming a source region in a selected portion of said silicon substrate; sequentially depositing an oxide layer and a BPSG layer after forming said source region; exposing a portion of said select gate, thereby forming a contact hole; and forming a word line on the resulting structure after forming said contact hole.
Claim 3
Dependent Claim
16 words
The method of claim 1, wherein said side wall insulating layer is formed in ONO structure.
Claim 4
Dependent Claim
19 words
The method of claim 1, wherein said word line is formed with any one of polysilicon, polycide or metal.
Claim 5
Dependent Claim
23 words
The method of claim 1, wherein said source region is formed by an ion implantation method using said select gate as a mask.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-03 | 2000-09-02 | 2001-03-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-03 | 2004-09-02 | 2005-03-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-03 | 2008-09-02 | 2009-03-04 | $7700.00 | Window Closed / Lapsed |