US5604888A — Emulation system employing motherboard and flexib…

Claim 1

Independent Claim 207 words

An emulation system for emulating a circuit design comprising: (a) a motherboard having a plurality of sockets, said sockets including first pin group locations electrically connected to an interconnect structure and second pin group locations electrically connected to a busing structure; and (b) at least one card with (i) pins arranged such that the card can be attached to a socket of said sockets, the pins including a first pin group arranged to contact the first pin group locations of a socket and a second pin group arranged to contact the second pin group locations of the socket, (ii) at least one field programmable gate array for emulating a portion of the circuit design, said at least one field programmable gate array including signal pins, some of the signal pins electrically connected to pins of the first pin group on the card, and (iii) a card controller chip, said card controller chip being electrically connected to control pins of the at least one field programmable gate array, the card controller chip loading configuration data into said at least one field programmable gate array, said card controller chip including control pins, some of the control pins electrically connected to pins of the first pin group on the card.

Claim 2

Dependent Claim 207 words

An emulation system for emulating a circuit design comprising: (a) a motherboard having a plurality of sockets, said sockets including first pin group locations electrically connected to an interconnect structure and second pin group locations electrically connected to a busing structure; and (b) at least one card with (i) pins arranged such that the card can be attached to a socket of said sockets, the pins including a first pin group arranged to contact the first pin group locations of a socket and a second pin group arranged to contact the second pin group locations of the socket, (ii) at least one field programmable gate array for emulating a portion of the circuit design, said at least one field programmable gate array including signal pins, some of the signal pins electrically connected to pins of the first pin group on the card, and (iii) a card controller chip, said card controller chip being electrically connected to control pins of the at least one field programmable gate array, the card controller chip loading configuration data into said at least one field programmable gate array, said card controller chip including control pins, some of the control pins electrically connected to pins of the first pin group on the card.

Claim 3

Dependent Claim 52 words

The emulation system of claim 1, wherein said field programmable gate array is of a type selected from a plurality of different types of field programmable gate arrays and wherein said card controller chip can be configured to load configuration data to each of the different types of field programmable gate arrays.

Claim 4

Dependent Claim 29 words

The emulation system of claim 2, wherein the card controller chip comprises another field programmable gate array, said another field programmable gate array being configurable through said busing structure.

Claim 5

Dependent Claim 38 words

The emulation system of claim 1, wherein said busing structure comprises a motherboard controller chip, said motherboard controller chip electrically connected to a host computer to load the configuration data to the card controller chips on the cards.

Claim 6

Dependent Claim 57 words

The emulation system of claim 1, further comprising an additional card attachable to said sockets, said additional cards including a core chip, said core chip being part of the emulated design, wherein, when the card is attached to a socket, pins of said core chip are electrically connected to the first pin group locations of the socket.

Claim 7

Dependent Claim 14 words

The emulation system of claim 5, wherein said core chip is a memory chip.

Claim 8

Dependent Claim 14 words

The emulation system of claim 5, wherein said core chip is a microprocessor chip.

Claim 9

Dependent Claim 67 words

The emulation system of claim 5, wherein said additional card further comprises an additional field programmable gate array attached to said busing structure, said additional field programmable gate array being electrically connected to pins of the core chip so that the core chip can be controlled from the busing structure and so that the state of some of the pins on the core chip can be determined.

Claim 10

Dependent Claim 48 words

The emulation system of claim 8, wherein said core chip can be controlled to output the state of at least one internal node of the core chip onto one of the core chip's pins so that the state of said node can be output on said busing structure.

Claim 11

Dependent Claim 37 words

The emulation system of claim 1, wherein said interconnect structure comprises an array of further field programmable gate array chips on the motherboards, and wherein said array is arrange to electrically interconnect pin locations on different sockets.

Claim 12

Dependent Claim 30 words

The emulation system of claim 1, wherein the card controller chip allows testing and fault simulation of the portion of the circuit design emulated on the field programmable gate array.

Claim 13

Dependent Claim 32 words

The emulation system of claim 1, further comprising a computer host connected to said busing system, said computer host being able to configure, test and do fault simulation on the emulation system.

Claim 14

Dependent Claim 25 words

The emulation system of claim 1, further comprising an additional motherboard with associated cards, said additional motherboard and said motherboard connected together by a rack.

Claim 15

Dependent Claim 141 words

An emulation system comprising: bus lines electrically connecting a chip footprint and a configurable interconnect chip, said chip footprint arranged such that the chip footprint can accept a plurality of different candidate types of field programmable gate array chips; said configurable interface chip configurable into one of a plurality of different configurations, each different configuration corresponding to one of said candidate types such that for each different type, the interface chip can be configured to control a field programmable gate array of that type over said bus lines; and a field programmable gate array of one of said different candidate of types placed in said chip footprint, said field programmable gate array able to emulate a portion of a circuit design, wherein the configurable interface chip is configured for the type of field programmable gate array placed in the chip footprint.

Claim 16

Dependent Claim 141 words

An emulation system comprising: bus lines electrically connecting a chip footprint and a configurable interconnect chip, said chip footprint arranged such that the chip footprint can accept a plurality of different candidate types of field programmable gate array chips; said configurable interface chip configurable into one of a plurality of different configurations, each different configuration corresponding to one of said candidate types such that for each different type, the interface chip can be configured to control a field programmable gate array of that type over said bus lines; and a field programmable gate array of one of said different candidate of types placed in said chip footprint, said field programmable gate array able to emulate a portion of a circuit design, wherein the configurable interface chip is configured for the type of field programmable gate array placed in the chip footprint.

Claim 17

Dependent Claim 81 words

The emulation system of claim 14 wherein said configurable interface chip, said bus line and said field programmable gate array are on a card, said card having pins arranged to fit into a socket of a motherboard; wherein said configurable interconnect chip is electrically connected to a busing structure on the motherboard; and wherein the field programmable gate array has pins, some of the pins of the field programmable gate array are electrically connected to an interconnect structure on the motherboard.

Claim 18

Dependent Claim 65 words

The emulation system of claim 14, further comprising additional field programmable gate arrays of said one of said different candidate types, said additional field programmable gate arrays are able to emulate another portion of the circuit design, said additional field programmable gate arrays are located in footprints connected to the bus lines, and wherein said configurable interface chip controls said additional field programmable gate arrays.

Claim 19

Dependent Claim 17 words

The emulation system of claim 16, wherein the configurable interface chip is connected to a host computer.

Claim 20

Dependent Claim 23 words

The emulation system of claim 17, further comprising an interconnect connecting some of the signal pins of the field programmable gate arrays together.

Claim 21

Dependent Claim 17 words

The emulation system of claim 18, wherein said interconnect comprises an array of field programmable gate arrays.

Claim 22

Dependent Claim 65 words

The emulation system of claim 14, wherein the plurality of different candidate types of field programmable gate array chips includes types having a control pin for the same function at different pin locations and wherein the configurable interface chip is configurable to supply signals to the control pin at different pin locations depending what type of field programmable gate array is in the chip footprint.

Claim 23

Independent Claim 194 words

A method of emulating a circuit comprising: providing a reconfigurable controller chip connected to a host processor, said reconfigurable controller chip connected by a bus structure to at least two field programmable gate arrays of a first type, said field programmable gate arrays having control pins; routing the reconfigurable controller chip so that control pins of the at least two field programmable gate arrays are accessible by said host processor; loading configuration data to the at least two field programmable gate arrays through the reconfigurable controller chip to emulate a portion of a circuit; replacing the at least two field programmable gate arrays with another at least two field programmable gate arrays of a second type having control pins, at least one being in a different pin location than the corresponding control pin on the field programmable gate arrays of the first type; rerouting the reconfigurable controller chip so that control pins of the another at least two field programmable gate arrays are accessible by said host processor; and loading configuration data to the another at least two field programmable gate arrays through the reconfigurable controller chip to emulate another portion of a circuit.

Claim 24

Independent Claim 194 words

A method of emulating a circuit comprising: providing a reconfigurable controller chip connected to a host processor, said reconfigurable controller chip connected by a bus structure to at least two field programmable gate arrays of a first type, said field programmable gate arrays having control pins; routing the reconfigurable controller chip so that control pins of the at least two field programmable gate arrays are accessible by said host processor; loading configuration data to the at least two field programmable gate arrays through the reconfigurable controller chip to emulate a portion of a circuit; replacing the at least two field programmable gate arrays with another at least two field programmable gate arrays of a second type having control pins, at least one being in a different pin location than the corresponding control pin on the field programmable gate arrays of the first type; rerouting the reconfigurable controller chip so that control pins of the another at least two field programmable gate arrays are accessible by said host processor; and loading configuration data to the another at least two field programmable gate arrays through the reconfigurable controller chip to emulate another portion of a circuit.

Claim 25

Dependent Claim 81 words

The method of claim 21, wherein the at least two field programmable gate arrays of the first type and the reconfigurable controller chip are provided on a card and said replacing step comprises replacing the at least two field programmable gate arrays with another at least two field programmable gate arrays of a second type on the daughter card, the method further comprising placing the card in a socket on a motherboard, the motherboard being electrically connected to the host processor.

Claim 26

Dependent Claim 33 words

The method of claim 22, wherein said configuration loading steps further comprises connecting some of the signal pins of the field programmable gate arrays together in an array of field programmable gate arrays.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2000-02-18	2000-08-19	2001-02-18	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2004-02-18	2004-08-19	2005-02-18	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2008-02-18	2008-08-19	2009-02-18	$7700.00	Window Closed / Lapsed

Emulation system employing motherboard and flexible daughterboards

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