Method and apparatus for performing error correction on data from an external memory

Claim 3

The method defined in claim 1 wherein the step of correcting the data includes correcting single bit errors in the data.

Claim 4

The method defined in claim 1 wherein the step of receiving includes receiving a plurality of blocks of data.

Claim 5

The method defined in claim 3 wherein the plurality of blocks are received in successive clock cycles.

Claim 6

The method defined in claim 3 wherein only one of said plurality of blocks includes the data desired by the requesting unit, and wherein the step of sending includes sending only said one of the plurality of blocks to said requesting unit.

Claim 9

The method defined in claim 6 wherein the step of correcting the data includes correcting single bit errors in the data.

Claim 10

The method defined in claim 6 wherein the corrected data is provided from the cache memory.

Claim 11

A processor for use in a computer system having at least one memory external to said processor, said processor comprising: an internal bus; an execution core coupled to the internal bus and executing instructions using data; a cache memory coupled to the internal bus for storing data for use by the processor; an error correction logic coupled to the internal bus and operable to perform error correction on data received from said at least one memory that has an error in parallel to the data being received and immediately used by the execution core; a controller coupled to the execution core and the error correction logic and operable to cause the execution core to be purged of results from the execution core operating with erroneous data and to cause the error correction logic to send corrected data to the cache memory in a clock cycle immediately subsequent to the execution core receiving the faulty data to enable the execution core to obtain the corrected data; and a reorder buffer having a plurality of entries storing data results from the execution core operating with erroneous data, wherein the reorder buffer invalidates said plurality of entries when the execution core is purged.

Claim 12

A processor for use in a computer system having at least one memory external to said processor, said processor comprising: an internal bus; an execution core coupled to the internal bus and executing instructions using data; a cache memory coupled to the internal bus for storing data for use by the processor; an error correction logic coupled to the internal bus and operable to perform error correction on data received from said at least one memory that has an error in parallel to the data being received and immediately used by the execution core; a controller coupled to the execution core and the error correction logic and operable to cause the execution core to be purged of results from the execution core operating with erroneous data and to cause the error correction logic to send corrected data to the cache memory in a clock cycle immediately subsequent to the execution core receiving the faulty data to enable the execution core to obtain the corrected data; and a reorder buffer having a plurality of entries storing data results from the execution core operating with erroneous data, wherein the reorder buffer invalidates said plurality of entries when the execution core is purged.

Claim 13

The processor defined in claim 9 wherein the processor obtains the data from said at least one memory in response to a data request, and further wherein the execution core obtains the corrected data in response to the data request being repeated.

Claim 14

The processor defined in claim 9 wherein the error correction logic is within bus controller logic within the processor.

Claim 15

The processor defined in claim 9 wherein the cache memory comprises an L1 cache memory.

Claim 16

The processor defined in claim 9 wherein said at least one memory comprises an L2 cache memory, such that said error correction logic performs error correction on data received from the L2 cache memory.

Claim 17

The processor defined in claim 9 wherein the error correction logic performs single bit error correction.

Claim 18

The processor defined in claim 9 further comprising staging logic coupled to the error correction logic and the controller to stage the corrected data for one clock.

Claim 19

A computer system comprising: a first bus for communicating information; a main memory coupled to the first bus; a second bus for communicating information; a first cache memory coupled to the second bus; a processor coupled to the first bus and the second bus, wherein the processor comprises an internal bus, an execution core coupled to the internal bus and executing instructions using data, a second cache memory coupled to the internal bus for storing data for use by the processor, an error correction logic coupled to the internal bus and operable to perform error correction on data received from an external source, and a reorder buffer having a plurality of entries; wherein the processor issues data requests to the first cache memory and upon receipt of data corresponding to the data requests, forwards data directly to the execution core via the internal bus for use therein while, in parallel, the error correction logic performs error correction on the data and corrects the data if the data has an error to produce error corrected data, and further wherein the processor further comprises a controller coupled to the execution core and the error correction logic and operable to cause the execution core to be purged of results from the execution core operating with faulty data and to cause the error correction logic to send corrected data to the second cache memory in a clock cycle immediately subsequent to the execution core receiving the faulty data to enable the execution core to obtain the corrected data, and wherein said the plurality of entries of the reorder buffer store data results from the execution core operating with faulty data, and wherein the reorder buffer invalidates said plurality of entries when the execution core is purged.

Claim 20

A computer system comprising: a first bus for communicating information; a main memory coupled to the first bus; a second bus for communicating information; a first cache memory coupled to the second bus; a processor coupled to the first bus and the second bus, wherein the processor comprises an internal bus, an execution core coupled to the internal bus and executing instructions using data, a second cache memory coupled to the internal bus for storing data for use by the processor, an error correction logic coupled to the internal bus and operable to perform error correction on data received from an external source, and a reorder buffer having a plurality of entries; wherein the processor issues data requests to the first cache memory and upon receipt of data corresponding to the data requests, forwards data directly to the execution core via the internal bus for use therein while, in parallel, the error correction logic performs error correction on the data and corrects the data if the data has an error to produce error corrected data, and further wherein the processor further comprises a controller coupled to the execution core and the error correction logic and operable to cause the execution core to be purged of results from the execution core operating with faulty data and to cause the error correction logic to send corrected data to the second cache memory in a clock cycle immediately subsequent to the execution core receiving the faulty data to enable the execution core to obtain the corrected data, and wherein said the plurality of entries of the reorder buffer store data results from the execution core operating with faulty data, and wherein the reorder buffer invalidates said plurality of entries when the execution core is purged.

Claim 21

The computer system defined in claim 16 wherein the execution core obtains the corrected data in response to a data request being repeated.

Claim 22

The computer system defined in claim 16 wherein the second cache memory comprises an L1 cache memory.

Claim 23

The computer system defined in claim 16 wherein the error correction logic performs single bit error correction.

Claim 24

The computer system defined in claim 16 wherein the processor further comprises staging logic coupled to the error correction logic and the controller to stage the corrected data for one clock.

Claim 25

A computer system comprising: a first bus for communicating information; a main memory coupled to the first bus; a second bus for communicating information; a first cache memory coupled to the second bus; a processor coupled to the first bus and the second bus, wherein the processor and first cache memory are contained in a single integrated circuit package, and wherein the first bus comprises a dedicated bus, said processor comprising an internal bus, an execution core coupled to the internal bus and executing instructions using data, a second cache memory coupled to the internal bus for storing data for use by the processor, and an error correction logic coupled to the internal bus and operable to perform error correction on data received from an external source; wherein the processor issues data requests to the first cache memory and upon receipt of data corresponding to the data requests, forwards data directly to the execution core via the internal bus for use therein while, in parallel, the error correction logic performs error correction on the data and corrects the data if the data has an error to produce error corrected data, and further wherein the processor further comprises a controller coupled to the execution core and the error correction logic and operable to cause the execution core to be purged of results from the execution core operating with faulty data and to cause the error correction logic to send corrected data to the second cache memory in a clock cycle immediately subsequent to the execution core receiving the faulty data to enable the execution core to obtain the corrected data.

Claim 26

A computer system comprising: a first bus for communicating information; a main memory coupled to the first bus; a second bus for communicating information; a first cache memory coupled to the second bus; a processor coupled to the first bus and the second bus, wherein the processor and first cache memory are contained in a single integrated circuit package, and wherein the first bus comprises a dedicated bus, said processor comprising an internal bus, an execution core coupled to the internal bus and executing instructions using data, a second cache memory coupled to the internal bus for storing data for use by the processor, and an error correction logic coupled to the internal bus and operable to perform error correction on data received from an external source; wherein the processor issues data requests to the first cache memory and upon receipt of data corresponding to the data requests, forwards data directly to the execution core via the internal bus for use therein while, in parallel, the error correction logic performs error correction on the data and corrects the data if the data has an error to produce error corrected data, and further wherein the processor further comprises a controller coupled to the execution core and the error correction logic and operable to cause the execution core to be purged of results from the execution core operating with faulty data and to cause the error correction logic to send corrected data to the second cache memory in a clock cycle immediately subsequent to the execution core receiving the faulty data to enable the execution core to obtain the corrected data.

Claim 27

The computer system defined in claim 21 wherein the processor further comprises a reorder buffer having a plurality of entries storing data results from the execution core operating with faulty data, and wherein the reorder buffer invalidates said plurality of entries when the execution core is purged.

Claim 28

The computer system defined in claim 16 or 21 wherein said first cache memory comprises an L2 cache memory, such that said error correction logic performs error correction on data received from the L2 cache memory.

Claim 29

A processor fabricated on an integrated circuit, the processor comprising: a plurality of pads; an error correction logic coupled to the plurality of pads and operable to perform error correction on erroneous data received on the plurality of pads; a multiplexor having a first input coupled to the plurality of pads and a second input coupled to an output of the error correction logic; a writeback bus coupled to the multiplexor; an execution core coupled to the writeback bus and operable to receive requested data directly from the plurality of pads for immediate use; a first level cache memory coupled to the writeback bus; and a controller coupled to the execution core and the multiplexor and operable to signal results generated by the execution core operating with erroneous data to be purged and operable to select error corrected data as an output of multiplexor onto the writeback bus in a clock cycle immediately subsequent to the execution core receiving the faulty data to enable the execution core to obtain the corrected data.

Claim 30

A processor fabricated on an integrated circuit, the processor comprising: a plurality of pads; an error correction logic coupled to the plurality of pads and operable to perform error correction on erroneous data received on the plurality of pads; a multiplexor having a first input coupled to the plurality of pads and a second input coupled to an output of the error correction logic; a writeback bus coupled to the multiplexor; an execution core coupled to the writeback bus and operable to receive requested data directly from the plurality of pads for immediate use; a first level cache memory coupled to the writeback bus; and a controller coupled to the execution core and the multiplexor and operable to signal results generated by the execution core operating with erroneous data to be purged and operable to select error corrected data as an output of multiplexor onto the writeback bus in a clock cycle immediately subsequent to the execution core receiving the faulty data to enable the execution core to obtain the corrected data.

Claim 31

The processor defined in claim 24 wherein the execution core receives the error corrected data in response to a repeated data request.

Claim 32

The processor defined in claim 24 wherein the error correction logic is within bus controller logic within the processor.

Claim 33

The processor defined in claim 24 wherein the error correction logic performs error correction on data received on the plurality of pads from an L2 cache memory.

Claim 34

The processor defined in claim 24 wherein the error correction logic performs single bit error correction.

Claim 35

The processor defined in claim 24 further comprising staging logic coupled to the error correction logic and the controller to stage the corrected data for one clock.