US5361267A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Scheme for error handling in a computer system
Assignee: Hewlett Packard Development Co LP
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Filing: 1992-04-24
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Granted: 1994-11-01
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Expires: 2012-04-24
Abstract
Abstract The present invention is directed to a control flow logic device for handling data received from a bus by a bus interface, in response to a bus read transaction, and transferred to a processor. The control flow logic includes an error checker to check data received from the bus for hard errors and parity errors and an ECC generator to generate an ECC for the received data, the ECC being forced to a bad ECC when a hard error is detected by the error checker and to a good ECC in the absence of a hard error. An error signal generator is utilized to generate and transmit an error signal to the processor when there is a hard error or a parity error in the received data and a data mover transmits the received data and the ECC to the processor.
Inventors
- 👤 Nitin D. Godiwala
- 👤 Barry A. Maskas
- 👤 Kurt M. Thaller
- 👤 Jeffrey A. Metzger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:47
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
159 words
A control flow logic device for handling data received from a bus by a bus interface, in response to a bus read transaction, and transferred to a processor, the control flow logic comprising: bus interface means for providing error checking and notification within a time cycle defined by an error free bus transaction, said bus interface means further comprising: an error checker to check data received from the bus for hard errors and parity errors; an ECC generator to generate an ECC for the received data, the ECC being forced to a bad ECC when a hard error is detected by the error checker and to a good ECC in the absence of a hard error; an error signal generator to generate and transmit an error signal to the processor when there is a hard error or a parity error in the received data; and a data mover to transmit the received data and the ECC to the processor.
Claim 2
Dependent Claim
159 words
A control flow logic device for handling data received from a bus by a bus interface, in response to a bus read transaction, and transferred to a processor, the control flow logic comprising: bus interface means for providing error checking and notification within a time cycle defined by an error free bus transaction, said bus interface means further comprising: an error checker to check data received from the bus for hard errors and parity errors; an ECC generator to generate an ECC for the received data, the ECC being forced to a bad ECC when a hard error is detected by the error checker and to a good ECC in the absence of a hard error; an error signal generator to generate and transmit an error signal to the processor when there is a hard error or a parity error in the received data; and a data mover to transmit the received data and the ECC to the processor.
Claim 3
Dependent Claim
37 words
The control flow logic device of claim 1, further comprising a cache memory coupled to the bus interface and the processor, the data mover transmitting the received data and the ECC to the cache memory for storage.
Claim 4
Independent Claim
142 words
A method for handling data received from a bus by a bus interface, in response to a bus read transaction, and transferred to a processor, the method comprising the steps of: performing, within a time defined by an error free bus transaction, error checking and data transfer operations, said error checking and data transfer further comprising the steps of: checking data received from the bus for hard errors and parity errors; generating an ECC for the received data, the ECC being forced to a bad ECC when a hard error is detected in the checking step and to a good ECC in the absence of a hard error; generating and transmitting an error signal to the processor when there is a hard error or a parity error in the received data; and transmitting the received data and the ECC to the processor.
Claim 5
Independent Claim
142 words
A method for handling data received from a bus by a bus interface, in response to a bus read transaction, and transferred to a processor, the method comprising the steps of: performing, within a time defined by an error free bus transaction, error checking and data transfer operations, said error checking and data transfer further comprising the steps of: checking data received from the bus for hard errors and parity errors; generating an ECC for the received data, the ECC being forced to a bad ECC when a hard error is detected in the checking step and to a good ECC in the absence of a hard error; generating and transmitting an error signal to the processor when there is a hard error or a parity error in the received data; and transmitting the received data and the ECC to the processor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-31 | 1998-05-02 | 1998-11-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-31 | 2002-05-02 | 2002-11-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-31 | 2006-05-02 | 2006-11-01 | $7700.00 | Window Closed / Lapsed |