US4604750A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pipeline error correction
Assignee: Hewlett Packard Development Co LP
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Filing: 1983-11-07
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Granted: 1986-08-05
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Expires: 2003-11-07
Abstract
Abstract In a data processing system, a memory (32) consists of data words and associated error-correction codes that are independently accessible; it is possible simultaneously to read a data word and write its associated error-correction code. This allows a memory-control circuit (30) immediately to store in the memory (32) a data word sent by a processor (10) while it is concurrently in the process of generating the error-correction code for that data word. The result is that the memory-control circuit (30) can subsequently fetch the newly stored data word before storage of its associated error-correction code is complete. This reduces delays involved in error-correction-code generation. The data word includes not only non-redundant information but also parity bits that both the processor (10) and the memory-control circuit (30) employ to determine whether a data word is correct. If the memory-control circuitry (30) determines that a word that it has forwarded to the processor (10) is incorrect, it immediately fetches the corresponding error-correction code and corrects the location in memory. Then, when the processor (10) finds that the parity is incorrect in the data word, it repeats its request for the data word in question, which the memory-control circuit (30) has corrected in the memory (32).
Inventors
- 👤 John C. Manton
- 👤 William F. Bruckert
- 👤 Alfred J. Dellicicchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 18:03
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1048
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
308 words
In a data processing system, the combination comprising: A. a memory circuit including a plurality of data locations for storing data, such as instructions and operands, and separate error-detection and error-correction codes associated with the data; B. processor means including: (i) means for generating memory-request signals that represent requests for the memory to send instructions and operands designated thereby; (ii) means for receiving the requested instructions and operands and the error-detection codes associated therewith and examining each received instruction and operand and the error-detection codes associated therewith to determine whether an error is present in that instruction or operand; and (iii) means for executing an instruction without applying it to error-correction circuitry if no error is detected in that instruction and any operand designated thereby and repeating the memory-request signal for that instruction if an error has been detected in that instruction or in an operand designated thereby; and C. memory control means connected to receive the memory-request signals from the processor means, the memory control means including: (i) means for operating the memory circuit to retrieve instructions and operands in response to the memory-request signals, and for operating the memory circuit to retrieve the error-correction code associated with an instruction or operand if an error is detected therein; (ii) means for examining the retrieved instructions and operands and their associated error-detection codes to determine whether errors exist therein; (iii) means for forwarding the instructions and operands and associated error-detection codes to the processor means without waiting for the determination of whether errors exist; and (iv) means for correcting any correctable detected error in accordance with that error-correction code, the data-processing system thereby providing for retrieval of correct instructions and operands without the delay required for error detection but still providing the capability for correction of errors in incorrect instructions and operands without correction by the processor means.
Claim 2
Dependent Claim
308 words
In a data processing system, the combination comprising: A. a memory circuit including a plurality of data locations for storing data, such as instructions and operands, and separate error-detection and error-correction codes associated with the data; B. processor means including: (i) means for generating memory-request signals that represent requests for the memory to send instructions and operands designated thereby; (ii) means for receiving the requested instructions and operands and the error-detection codes associated therewith and examining each received instruction and operand and the error-detection codes associated therewith to determine whether an error is present in that instruction or operand; and (iii) means for executing an instruction without applying it to error-correction circuitry if no error is detected in that instruction and any operand designated thereby and repeating the memory-request signal for that instruction if an error has been detected in that instruction or in an operand designated thereby; and C. memory control means connected to receive the memory-request signals from the processor means, the memory control means including: (i) means for operating the memory circuit to retrieve instructions and operands in response to the memory-request signals, and for operating the memory circuit to retrieve the error-correction code associated with an instruction or operand if an error is detected therein; (ii) means for examining the retrieved instructions and operands and their associated error-detection codes to determine whether errors exist therein; (iii) means for forwarding the instructions and operands and associated error-detection codes to the processor means without waiting for the determination of whether errors exist; and (iv) means for correcting any correctable detected error in accordance with that error-correction code, the data-processing system thereby providing for retrieval of correct instructions and operands without the delay required for error detection but still providing the capability for correction of errors in incorrect instructions and operands without correction by the processor means.
Claim 3
Dependent Claim
143 words
A combination as defined in claim 1 wherein: A. the memory circuit is organized to permit instructions and operands to be stored and retrieved separately from their associated error-correction codes; B. the processor means is connected to the memory control means to send data words to the memory control means for storage in the memory circuit; C. the memory control means is connected to receive the data words from the processor means and includes means for generating an associated error-correction code from each received data word; D. the means for operating the memory circuit operates the memory circuit to store the data word therein without waiting for generation of its associated error-correction code to be completed and subsequently stores the associated error-correction code, the data word thereby being ready for retrieval from the memory circuit before its associated error-correction code has been stored.
Claim 4
Dependent Claim
34 words
A combination as defined in claim 2 wherein the memory control circuit operates the memory circuit to retrieve the error-correction code associated with an instruction or operand only if an error is detected therein.
Claim 5
Dependent Claim
34 words
A combination as defined in claim 1 wherein the memory control circuit operates the memory circuit to retrieve the error-correction code associated with an instruction or operand only if an error is detected therein.
Claim 6
Dependent Claim
215 words
In a data processing system, the combination comprising: A. a memory circuit including a plurality of data locations for storing data, such as instructions and operands. and error-correction codes associated with the data, the memory circuit being organized to permit instructions and operands to be stored and retrieved separately from their associated error-correction codes; B. execution means for generating memory-request signals that represent requests for the memory to send instructions and operands designated thereby, for receiving the requested instructions and operands, and for executing instructions; and C. memory control means connected to receive the memory-request signals from the execution means and adapted to receive data words, the memory control means including: (i) means for generating from a received data word an error-correction code associated therewith; (ii) means for operating the memory circuit to store a received data word therein without waiting for generation of its associated error-correction code to be completed, subsequently operating the memory circuit to store the associated error-correction code, and further operating the memory circuit to retrieve instructions and operands in response to the memory-request signals; and (iii) means for forwarding those instructions and operands to the execution means, retrieval and forwarding of data for the execution means thereby being afforded without a delay resulting from generation of the associated error-correction codes.
Claim 7
Dependent Claim
215 words
In a data processing system, the combination comprising: A. a memory circuit including a plurality of data locations for storing data, such as instructions and operands. and error-correction codes associated with the data, the memory circuit being organized to permit instructions and operands to be stored and retrieved separately from their associated error-correction codes; B. execution means for generating memory-request signals that represent requests for the memory to send instructions and operands designated thereby, for receiving the requested instructions and operands, and for executing instructions; and C. memory control means connected to receive the memory-request signals from the execution means and adapted to receive data words, the memory control means including: (i) means for generating from a received data word an error-correction code associated therewith; (ii) means for operating the memory circuit to store a received data word therein without waiting for generation of its associated error-correction code to be completed, subsequently operating the memory circuit to store the associated error-correction code, and further operating the memory circuit to retrieve instructions and operands in response to the memory-request signals; and (iii) means for forwarding those instructions and operands to the execution means, retrieval and forwarding of data for the execution means thereby being afforded without a delay resulting from generation of the associated error-correction codes.
Claim 8
Dependent Claim
76 words
A combination as defined in claim 5 wherein: A. the memory circuit is operable for simultaneous retrieval of a data word and storage of its associated error-correction code; and B. the means for operating the memory circuit is operable to respond to memory-request signals by fetching a data word while it is simultaneously operating the memory circuit to store the associated error-correction code, fetching of data words thereby taking place without delaying storage of error-correction codes.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-08-04 | 1990-02-03 | 1990-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-08-04 | 1994-02-03 | 1994-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-08-04 | 1998-02-03 | 1998-08-05 | $7700.00 | Window Closed / Lapsed |