Out of cycle error correction apparatus

Claim 2

In an execution control store unit of a data processing system, apparatus for providing an accurate data group to an instruction buffer, said apparatus comprising: memory means for storing data groups to be provided to said instruction buffer; register means for storing a data group; coupling means for applying a selected data group from said memory means during a first timing period of said data processing system to instruction buffer and to said register means; error correction and detection means coupled to said register means and said coupling means; said error correction and detection means detecting during said first timing period at least one correctable error in said selected data group; said error correction and detection means correcting said selected data group when said correctable error is detected, said error correction and detection means generating a correctable error signal when said correctable error is detected, wherein said coupling means applies said corrected selected data group to said instruction buffer during a next timing cycle when said correctable error signal is generated, said correctable error signal causing said corrected selected data group to replace said selected data group in said instruction buffer, said coupling means applying a next selected data group to said instruction buffer when said correctable error signal is not generated.

Claim 3

The apparatus of claim 1 wherein said error correction and detection apparatus can detect the presence of an uncorrectable error in said data groups, said error correction and detection apparatus generating an abort signal in response to detection of said uncorrectable signal.

Claim 6

In a data processing unit, apparatus for providing accurate data groups to an instruction buffer comprising: a system clock for generating a sequence of timing periods; a memory unit for storing a sequence of selected data groups; error correction and detection (edac) means, said edac means providing a correctable error signal when a correctable error is detected by said means; and switching means responsive to said system clock and to said correctable error signal; said switching means applying a first selected data group from said memory to said instruction buffer and to said edac means during a first timing period, said edac means generating a correctable error signal when at least one correctable error is found in said first data group, said edac means correcting said correctable error in said data groups when said correctable error is found, said switching means applying a next data group for said memory unit to said instruction buffer during a second period when no correctable error signal is generated by said edac means, said switching means applying said corrected first error group to said instruction buffer replacing said selected data group when a correctable error signal is generated.

Claim 7

In a data processing unit, apparatus for providing accurate data groups to an instruction buffer comprising: a system clock for generating a sequence of timing periods; a memory unit for storing a sequence of selected data groups; error correction and detection (edac) means, said edac means providing a correctable error signal when a correctable error is detected by said means; and switching means responsive to said system clock and to said correctable error signal; said switching means applying a first selected data group from said memory to said instruction buffer and to said edac means during a first timing period, said edac means generating a correctable error signal when at least one correctable error is found in said first data group, said edac means correcting said correctable error in said data groups when said correctable error is found, said switching means applying a next data group for said memory unit to said instruction buffer during a second period when no correctable error signal is generated by said edac means, said switching means applying said corrected first error group to said instruction buffer replacing said selected data group when a correctable error signal is generated.

Claim 8

The apparatus of claim 4 wherein said edac means further includes apparatus for generating an abort signal when an uncorrectable error is detected, said abort signal causing said selected data group to be disregarded by said data processing unit.

Claim 9

The apparatus of claim 4 wherein said next data group is applied by said switching means to said instruction buffer during a third timing period when said correctable error signal is generated.

Claim 10

In a data processing unit having a central processing unit, said central processing unit controlling the transfer of a sequence of data groups from a memory unit to an instruction buffer associated with said central processing unit; said data groups having included therewith data bits permitting detection and correction of errors in said data group; apparatus for providing accurate data groups to said instruction buffer comprising: clock means for providing a series of timing intervals of predetermined duration; error detection and correction (edac) means for identifying at least one correctable error in each of said data groups, said edac means generating a correctable error signal upon identification of said correctable error, said edac means providing a corrected data group when a correctable error is detected; switching means coupled to said edac means, said clock means and said instruction buffer, said switching means applying a selected data group to said instruction buffer and to said edac means during a selected timing period; said edac means providing said correctable error signal to said central processing unit when a correctable error is identified in said selected data group, said switching means providing a next data group selected from said sequence of data groups during a next consecutive selected timing interval when said correctable error signal is not present, said switching means providing a corrected selected data group to said instruction buffer during said next selected timing interval when said correctable error signal is generated, said next data group being applied to said instruction buffer during a third selected timing interval when said correctable signal is generated by said next data group.

Claim 11

In a data processing unit having a central processing unit, said central processing unit controlling the transfer of a sequence of data groups from a memory unit to an instruction buffer associated with said central processing unit; said data groups having included therewith data bits permitting detection and correction of errors in said data group; apparatus for providing accurate data groups to said instruction buffer comprising: clock means for providing a series of timing intervals of predetermined duration; error detection and correction (edac) means for identifying at least one correctable error in each of said data groups, said edac means generating a correctable error signal upon identification of said correctable error, said edac means providing a corrected data group when a correctable error is detected; switching means coupled to said edac means, said clock means and said instruction buffer, said switching means applying a selected data group to said instruction buffer and to said edac means during a selected timing period; said edac means providing said correctable error signal to said central processing unit when a correctable error is identified in said selected data group, said switching means providing a next data group selected from said sequence of data groups during a next consecutive selected timing interval when said correctable error signal is not present, said switching means providing a corrected selected data group to said instruction buffer during said next selected timing interval when said correctable error signal is generated, said next data group being applied to said instruction buffer during a third selected timing interval when said correctable signal is generated by said next data group.

Claim 12

The apparatus of claim 7 wherein said edac means generates an abort signal to said central processing unit when an uncorrectable error is identified in said data group.