US3693153A
Expired / Lapsed
US
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Parity check apparatus and method for minicomputers
Assignee: AT&T Inc
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Filing: 1971-07-09
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Granted: 1972-09-19
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Expires: 1991-07-09
Abstract
Abstract Apparatus for facilitating the detection and correction of errors in data stored in and communicated to (and from) a small data processor is disclosed. A simple parity checking circuit facilitates a program-controlled error detection process.
Inventors
- 👤 Peter Ernest Rosenfeld
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 00:36
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 39
Claim 1
Independent Claim
157 words
Apparatus comprising A a data processor comprising 1. an addRessable memory storing a plurality of program and data words, 2. addressing means for determining the location in said memory from which words are to be read, 3. means responsive to said addressing means for accessing program and data words, 4. first and second registers, 5. means for temporarily storing data read from said memory in said first register, 6. means for temporarily storing indications of program words read from said memory in said second register, 7. control means responsive to selected ones of said indications for generating control signals, and 8. a parity check circuit responsive to said control signals for generating an output signal whenever the contents of said first register assumes a predetermined parity condition; and B. modifying means responsive to said signal generated by said parity check circuit for modifying the state of said addressing means, thereby altering the sequence of accessing of words.
Claim 2
Dependent Claim
157 words
Apparatus comprising A a data processor comprising 1. an addRessable memory storing a plurality of program and data words, 2. addressing means for determining the location in said memory from which words are to be read, 3. means responsive to said addressing means for accessing program and data words, 4. first and second registers, 5. means for temporarily storing data read from said memory in said first register, 6. means for temporarily storing indications of program words read from said memory in said second register, 7. control means responsive to selected ones of said indications for generating control signals, and 8. a parity check circuit responsive to said control signals for generating an output signal whenever the contents of said first register assumes a predetermined parity condition; and B. modifying means responsive to said signal generated by said parity check circuit for modifying the state of said addressing means, thereby altering the sequence of accessing of words.
Claim 3
Dependent Claim
16 words
addressing means for determining the location in said memory from which words are to be read,
Claim 4
Dependent Claim
16 words
addressing means for determining the location in said memory from which words are to be read,
Claim 5
Dependent Claim
25 words
addressing means for determining the location in said memory from which program words are to be read and into which data words may be entered,
Claim 6
Dependent Claim
25 words
addressing means for determining the location in said memory from which program words are to be read and into which data words may be entered,
Claim 7
Dependent Claim
31 words
Apparatus according to claim 1 wherein said parity check circuit comprises means for generating an output signal whenever said contents of said first register give rise to an odd parity condition.
Claim 8
Dependent Claim
30 words
whenever said data word does not have said prescribed parity condition a. halting the transfer directed at step (A), and b. skipping said instruction specifying a return to step (A).
Claim 9
Dependent Claim
30 words
whenever said data word does not have said prescribed parity condition a. halting the transfer directed at step (A), and b. skipping said instruction specifying a return to step (A).
Claim 10
Dependent Claim
39 words
Apparatus according to claim 1 wherein said addressing means comprises a program counter, and wherein said modifying means comprises means for incrementing said counter, thereby effecting a skipping of one or more locations in the course of accessing words.
Claim 11
Dependent Claim
10 words
means responsive to said addressing means for accessing program words,
Claim 12
Dependent Claim
10 words
means responsive to said addressing means for accessing program words,
Claim 13
Dependent Claim
12 words
means responsive to said addressing means for accessing program and data words,
Claim 14
Dependent Claim
12 words
means responsive to said addressing means for accessing program and data words,
Claim 15
Dependent Claim
4 words
first and second registers,
Claim 16
Dependent Claim
4 words
first and second registers,
Claim 17
Dependent Claim
4 words
first and second registers,
Claim 18
Dependent Claim
4 words
first and second registers,
Claim 19
Dependent Claim
21 words
Apparatus for checking the accuracy of and for storing a sequence of input data words comprising A. a data processor comprising
Claim 20
Dependent Claim
21 words
Apparatus for checking the accuracy of and for storing a sequence of input data words comprising A. a data processor comprising
Claim 21
Dependent Claim
31 words
Apparatus according to claim 4 wherein said parity check circuit comprises means for generating an output signal whenever said contents of said first register give rise to an odd parity condition.
Claim 22
Dependent Claim
12 words
means for temporarily storing an input data word in said first register,
Claim 23
Dependent Claim
12 words
means for temporarily storing an input data word in said first register,
Claim 24
Dependent Claim
13 words
means for temporarily storing data read from said memory in said first register,
Claim 25
Dependent Claim
13 words
means for temporarily storing data read from said memory in said first register,
Claim 26
Dependent Claim
16 words
means for temporarily storing indications of program words read from said memory in said second register,
Claim 27
Dependent Claim
16 words
means for temporarily storing indications of program words read from said memory in said second register,
Claim 28
Dependent Claim
19 words
means for temporarily storing an indication of a program signal read from said memory in said second register, and
Claim 29
Dependent Claim
19 words
means for temporarily storing an indication of a program signal read from said memory in said second register, and
Claim 30
Dependent Claim
50 words
In a stored program data processor comprising a memory, the machine method for monitoring the bidirectional transfer of data words to said memory comprising the steps of A. executing an instruction directing the transfer of a data word, B. determining whether said data word has a prescribed parity condition, and
Claim 31
Dependent Claim
50 words
In a stored program data processor comprising a memory, the machine method for monitoring the bidirectional transfer of data words to said memory comprising the steps of A. executing an instruction directing the transfer of a data word, B. determining whether said data word has a prescribed parity condition, and
Claim 32
Dependent Claim
13 words
control means responsive to selected ones of said indications for generating control signals,
Claim 33
Dependent Claim
13 words
control means responsive to selected ones of said indications for generating control signals,
Claim 34
Dependent Claim
14 words
control means responsive to selected ones of said indications for generating control signals, and
Claim 35
Dependent Claim
14 words
control means responsive to selected ones of said indications for generating control signals, and
Claim 36
Dependent Claim
56 words
a parity check circuit responsive to said control signals for generating an output signal whenever the contents of said first register assumes a predetermined parity condition; and B. modifying means responsive to said signal generated by said parity check circuit for modifying the state of said addressing means, thereby altering the sequence of accessing of words.
Claim 37
Dependent Claim
56 words
a parity check circuit responsive to said control signals for generating an output signal whenever the contents of said first register assumes a predetermined parity condition; and B. modifying means responsive to said signal generated by said parity check circuit for modifying the state of said addressing means, thereby altering the sequence of accessing of words.
Claim 38
Dependent Claim
47 words
a parity check circuit responsive to said control signals for generating an output signal whenever the contents of said first register assumes a predetermined parity condition; and B. means responsive to said signal generated by said parity check circuit for modifying the state of said addressing means.
Claim 39
Dependent Claim
47 words
a parity check circuit responsive to said control signals for generating an output signal whenever the contents of said first register assumes a predetermined parity condition; and B. means responsive to said signal generated by said parity check circuit for modifying the state of said addressing means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-09-19 | 1976-03-20 | 1976-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-09-19 | 1980-03-20 | 1980-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-09-19 | 1984-03-20 | 1984-09-19 | $7700.00 | Window Closed / Lapsed |