US3566093A
Expired / Lapsed
US
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Diagnostic method and implementation for data processors
Assignee: Honeywell Inc
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Filing: 1968-03-29
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Granted: 1971-02-23
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Expires: 1988-03-29
Abstract
Abstract The addition of means for selectively complementing parity signals provides a way of flagging selected words or locations in a memory of an electronic data processor. The parity error signal can then be used in diagnostic routines for signaling erroneous access to a memory location or to provide a distinctive synchronization signal for test equipment while the memory is cycled through a loop including locations under test.
Inventors
- 👤 Thomas F Joyce
- 👤 John J Bradley
- 👤 Richard A Lemay
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 12:23
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1012; G06F11/1032
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
88 words
A digital system comprising a memory store having a plurality of addressable word storage locations; means to read a word from an addressed location during a read mode; means to write a word into an addressed location during a write mode; a parity generator for providing a parity bit with a word written in; a parity checker for checking the parity of a word addressed; and the combination with said parity generator of means to selectively complement the parity bit provided with a word into an addressed location.
Claim 2
Dependent Claim
88 words
A digital system comprising a memory store having a plurality of addressable word storage locations; means to read a word from an addressed location during a read mode; means to write a word into an addressed location during a write mode; a parity generator for providing a parity bit with a word written in; a parity checker for checking the parity of a word addressed; and the combination with said parity generator of means to selectively complement the parity bit provided with a word into an addressed location.
Claim 3
Dependent Claim
31 words
an output connection terminal for connecting the output of said parity checker as a synchronizing trigger to test equipment for use in analyzing the electrical operation of said data processing system.
Claim 4
Dependent Claim
31 words
an output connection terminal for connecting the output of said parity checker as a synchronizing trigger to test equipment for use in analyzing the electrical operation of said data processing system.
Claim 5
Dependent Claim
6 words
a write mode of operation; and
Claim 6
Dependent Claim
6 words
a write mode of operation; and
Claim 7
Dependent Claim
107 words
A digital memory system comprising a memory store having a plurality of addressable word storage locations; means to read a word from an addressed location during a read mode; means to write a word into an addressed location during a write mode; a parity generator for providing a parity bit with a word written in; a parity checker for checking the parity of a word read out; means associated with said parity generator to selectively complement the parity bit provided with a word written into an addressed location and means associated with said parity checker for signalling that a word with a complemented parity bit is accessed.
Claim 8
Dependent Claim
107 words
A digital memory system comprising a memory store having a plurality of addressable word storage locations; means to read a word from an addressed location during a read mode; means to write a word into an addressed location during a write mode; a parity generator for providing a parity bit with a word written in; a parity checker for checking the parity of a word read out; means associated with said parity generator to selectively complement the parity bit provided with a word written into an addressed location and means associated with said parity checker for signalling that a word with a complemented parity bit is accessed.
Claim 9
Dependent Claim
39 words
A digital memory system according to claim 2 in which said means associated with said parity checker for signalling the complemented parity bit comprises means for selectively signalling the complemented parity bit only during a write mode of operation.
Claim 10
Dependent Claim
7 words
both write and read modes of operation.
Claim 11
Dependent Claim
7 words
both write and read modes of operation.
Claim 12
Dependent Claim
38 words
A memory system according to claim 2 in which said means associated with said parity checker for signalling the complemented parity comprises means to signal the complemented parity during only a selected one of the following operational conditions:
Claim 13
Dependent Claim
30 words
A digital memory system according to claim 4 in which selection of the conditions under which the complemented parity bit is signalled is provided by a manually operated selector switch.
Claim 14
Dependent Claim
41 words
A digital memory system according to claim 2 in which said means to selectively complement the parity bit comprises a manually operable selector switch connected to switch an electrical inverter in and out of the output path of said parity generator.
Claim 15
Dependent Claim
35 words
A digital memory system according to claim 2 in which said means associated with said parity checker for signalling the complemented parity bit is connected to means for halting the operation of said memory system.
Claim 16
Dependent Claim
87 words
An electronic data processing system comprising a memory for storing data words consisting of digital bits; means to write data words into said memory; means to read data words from said memory; a parity generator for adding parity bits to data words written into said memory; a parity checker for checking parity bits of data words read out from said memory; and means to selectively complement the parity added to a data word from said parity generator and provide a faulty parity detectable by said parity checker.
Claim 17
Dependent Claim
87 words
An electronic data processing system comprising a memory for storing data words consisting of digital bits; means to write data words into said memory; means to read data words from said memory; a parity generator for adding parity bits to data words written into said memory; a parity checker for checking parity bits of data words read out from said memory; and means to selectively complement the parity added to a data word from said parity generator and provide a faulty parity detectable by said parity checker.
Claim 18
Dependent Claim
38 words
An electronic data processing system according to claim 8 in which the output of said parity checker is connected to a means for applying a signal to circuitry that will halt the operation of said data processing system.
Claim 19
Dependent Claim
37 words
An electronic data processing system according to claim 8 in which the output of said parity checker is connected to an output connector terminal adapted to apply a synchronizing trigger output for use with diagnostic test equipment.
Claim 20
Dependent Claim
23 words
An electronic data processing system according to claim 8 in which the output of said parity checker is selectively connected to one of:
Claim 21
Dependent Claim
27 words
An electronic data processing system according to claim 11 in which selection of the output connections for said parity checker is made by a manually operable switch.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-02-22 | 1974-08-24 | 1975-02-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-02-22 | 1978-08-24 | 1979-02-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-02-22 | 1982-08-24 | 1983-02-23 | $7700.00 | Window Closed / Lapsed |