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US5604145A
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Method of manufacturing DRAM capable of randomly inputting/outputting memory information at random
Assignee: Mitsubishi Electric Corp
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Filing: 1995-06-06
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Granted: 1997-02-18
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Expires: 2015-06-06
Abstract
Abstract Transfer gate transistors are formed on a main surface of a semiconductor substrate. The transfer gate transistors have impurity regions for serving as source/drain regions. A first interlayer insulating film having a substantially flat upper surface is formed to cover the transfer gate transistors. The first interlayer insulating film is provided with contact holes reaching the impurity regions. Plugs are formed in the contact holes. Capacitors are only formed on the flat upper surface of the first interlayer insulating film. Lower electrodes of the capacitors and the plugs are electrically connected with each other through barrier layers. Thus, it is possible to improve capacitances of capacitors in a DRAM.
Inventors
- 👤 Yasushi Hashizume
- 👤 Hiroki Shinkawata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 05:18
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
211 words
A method of manufacturing a semiconductor memory device, comprising: a step of forming an impurity region of a second conductivity type in a main surface of a semiconductor substrate of a first conductivity type; a step of forming a first interlayer insulating film having first and second portions on said main surface of said semiconductor substrate; a step of forming a stacked structure of a first electrode, a high dielectric film consisting of a material having a high dielectric constant, and a second electrode on the first portion of said first interlayer insulating film; a step of forming a second interlayer insulating film on the first and second portions of said first interlayer insulating film covering said stacked structure disposed on the first portion of said first interlayer insulating film; a step of forming a first contact hole penetrating through said first and second interlayer insulating films to reach said impurity region and forming a plug electrode therein; a step of forming a second contact hole in said second interlayer insulating film to reach a surface of said second electrode; and a step of forming a conductor part on said plug electrode and in said second contact hole for electrically connecting said second electrode and said impurity region with each other.
Claim 2
Independent Claim
211 words
A method of manufacturing a semiconductor memory device, comprising: a step of forming an impurity region of a second conductivity type in a main surface of a semiconductor substrate of a first conductivity type; a step of forming a first interlayer insulating film having first and second portions on said main surface of said semiconductor substrate; a step of forming a stacked structure of a first electrode, a high dielectric film consisting of a material having a high dielectric constant, and a second electrode on the first portion of said first interlayer insulating film; a step of forming a second interlayer insulating film on the first and second portions of said first interlayer insulating film covering said stacked structure disposed on the first portion of said first interlayer insulating film; a step of forming a first contact hole penetrating through said first and second interlayer insulating films to reach said impurity region and forming a plug electrode therein; a step of forming a second contact hole in said second interlayer insulating film to reach a surface of said second electrode; and a step of forming a conductor part on said plug electrode and in said second contact hole for electrically connecting said second electrode and said impurity region with each other.
Claim 3
Dependent Claim
40 words
A method of manufacturing a semiconductor memory device in accordance with claim 1, wherein said step of forming said high dielectric film includes a step of forming said high dielectric film at a temperature of at least about 600° C.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-18 | 2000-08-19 | 2001-02-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-18 | 2004-08-19 | 2005-02-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-18 | 2008-08-19 | 2009-02-18 | $7700.00 | Window Closed / Lapsed |