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US5603066A
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Method of flagging the completion of a second command before the completion of a first command from the same initiator in a SCSI controller
Assignee: Microsemi Storage Solutions Inc
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Filing: 1995-06-05
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Granted: 1997-02-11
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Expires: 2015-06-05
Abstract
Abstract A hard disk controller integrated circuit of a SCSI target device comprises a sequencer which causes a SCSI bus to transition from a command bus phase to a data transfer bus phase during execution of an autoread or an autowrite SCSI command without waiting for a communication from a microprocessor of the SCSI target device. In some embodiments, the command is determined to be either an autotransfer command or a non-autotransfer command. If the command is a non-autotransfer command, then the sequencer does not proceed directly to the data transfer phase but rather requires microprocessor intervention before proceeding to the data transfer phase. In some embodiments, an autotransfer command (such as an autoread or an autowrite command) is carried out by the disk drive controller integrated circuit with only two interrupts being generated to the microprocessor: one after receiving the autotransfer command from the initiator; and one after data transfer of the autotransfer command is complete. The hard disk controller integrated circuit automatically sends the status byte and command complete message if there is no potential queue tag collision as indicated by a cleared tag not okay flag.
Inventors
- 👤 Shahe H. Krakirian
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 23:56
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/06; G06F3/0601; G06F3/0602; G06F3/061; G06F13/00; G06F13/10; G06F13/12; G06F13/124; G06F13/126; G06F13/38; G06F13/382; G06F13/385; G06F3/0628; G06F3/0655; G06F3/0659; G06F3/0668; G06F3/0671; G06F3/0673; G06F3/0674; G06F3/0676
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
243 words
A method of transferring data from a SCSI bus to a target device, the target device comprising a processor and a disk controller integrated circuit, comprising the steps of: (a) receiving a SCSI write command into a memory of the disk controller integrated circuit, said SCSI write command comprising transfer length information indicative of a number of blocks of data; (b) said disk controller integrated circuit transferring said number of blocks of data from said SCSI bus to a buffer memory of said target device, said disk controller integrated circuit proceeding from said receiving step (a) to said transferring said number of blocks of data of step (b) without waiting for a communication from said processor; (c) receiving a queue tag of said SCSI write command into said disk controller integrated circuit; (d) setting a first flag in said disk controller integrated circuit when a first SCSI command is received from an initiator; (e) setting a second flag in said disk controller integrated circuit when a second SCSI command is received from the same initiator if said first flag is set; and (f) if said second flag is cleared at a point in time after said transferring of said number of blocks of data has started but before said transferring of said number of blocks is completed, outputting a status byte and a command complete message byte from said disk controller integrated circuit following said transferring of said number of blocks of data.
Claim 2
Independent Claim
243 words
A method of transferring data from a SCSI bus to a target device, the target device comprising a processor and a disk controller integrated circuit, comprising the steps of: (a) receiving a SCSI write command into a memory of the disk controller integrated circuit, said SCSI write command comprising transfer length information indicative of a number of blocks of data; (b) said disk controller integrated circuit transferring said number of blocks of data from said SCSI bus to a buffer memory of said target device, said disk controller integrated circuit proceeding from said receiving step (a) to said transferring said number of blocks of data of step (b) without waiting for a communication from said processor; (c) receiving a queue tag of said SCSI write command into said disk controller integrated circuit; (d) setting a first flag in said disk controller integrated circuit when a first SCSI command is received from an initiator; (e) setting a second flag in said disk controller integrated circuit when a second SCSI command is received from the same initiator if said first flag is set; and (f) if said second flag is cleared at a point in time after said transferring of said number of blocks of data has started but before said transferring of said number of blocks is completed, outputting a status byte and a command complete message byte from said disk controller integrated circuit following said transferring of said number of blocks of data.
Claim 3
Dependent Claim
31 words
The method of claim 1, further comprising the step of: clearing said second flag using said processor of said target after said setting step (d) but before said outputting step (f).
Claim 4
Dependent Claim
44 words
The method of claim 1, wherein said target device is not disconnected from said SCSI bus at any time between said transferring of said number of data blocks being completed and said command complete message byte being output from said disk controller integrated circuit.
Claim 5
Dependent Claim
203 words
A disk drive device coupled to a SCSI bus, comprising: a processor; and a disk controller integrated circuit, said disk controller integrated circuit comprising: a sequencer; and a memory containing a plurality of instructions executable by said sequencer, at least one of said instructions having a branch condition, said sequencer causing said SCSI bus to transition from a command bus phase to a data transfer bus phase without waiting for a communication from said processor when said branch condition is true, wherein said branch condition is true if a SCSI command being executed by said sequencer is an autotransfer command, said branch condition being false if said SCSI command being executed by said sequencer is not an autotransfer command, wherein said disk controller integrated circuit comprises a first flag bit which is set when a first SCSI command is received from an initiator and wherein said disk controller integrated circuit comprises a second flag bit which is set when a second SCSI command is received from the said initiator if said first flag is set wherein said sequencer causes a SCSI status byte and a SCSI command complete message byte to be output onto said SCSI bus if said second flag is cleared.
Claim 6
Dependent Claim
203 words
A disk drive device coupled to a SCSI bus, comprising: a processor; and a disk controller integrated circuit, said disk controller integrated circuit comprising: a sequencer; and a memory containing a plurality of instructions executable by said sequencer, at least one of said instructions having a branch condition, said sequencer causing said SCSI bus to transition from a command bus phase to a data transfer bus phase without waiting for a communication from said processor when said branch condition is true, wherein said branch condition is true if a SCSI command being executed by said sequencer is an autotransfer command, said branch condition being false if said SCSI command being executed by said sequencer is not an autotransfer command, wherein said disk controller integrated circuit comprises a first flag bit which is set when a first SCSI command is received from an initiator and wherein said disk controller integrated circuit comprises a second flag bit which is set when a second SCSI command is received from the said initiator if said first flag is set wherein said sequencer causes a SCSI status byte and a SCSI command complete message byte to be output onto said SCSI bus if said second flag is cleared.
Claim 7
Dependent Claim
17 words
The disk drive device of claim 4, wherein said second flag bit is clearable by said processor.
References Cited (Backward Citations)
US4142234A
Cited
US4503499A
Cited
US4901232A
Cited
US5230048A
Cited
US4815030A
Cited
US4843544A
Cited
US4965801A
Cited
US5379379A
Cited
US5022059A
Cited
US5247665A
Cited
US5129072A
Cited
US5195100A
Cited
US5233692A
Cited
US5454085A
Cited
US5325510A
Cited
US5421014A
Cited
US5274783A
Cited
US5404549A
Cited
US5367647A
Cited
US5450546A
Cited
US5463743A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-11 | 2000-08-12 | 2001-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-11 | 2004-08-12 | 2005-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-11 | 2008-08-12 | 2009-02-11 | $7700.00 | Window Closed / Lapsed |