US5325510A
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US
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Multiprocessor system and architecture with a computation system for minimizing duplicate read requests
Assignee: Texas Instruments Inc
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Filing: 1993-07-15
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Granted: 1994-06-28
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Expires: 2013-07-15
Abstract
Abstract Hierarchical multiprocessors systems with common level expansion modules. The invention includes an architecture for such multiprocessor system. One facet of such multiprocessor system including a memory control system for minimizing duplicate read requests comprising: a plurality of processing systems; a bus connecting the processing systems; a memory for storing variables; circuitry operable for receiving read requests through the bus from other processing systems; a memory for queuing incoming read requests, wherein the memory for queuing incoming read requests is connected to the circuitry operable for receiving read requests; a memory for queuing outgoing read requests, wherein the memory for queuing outgoing read requests is connected to bus and the memory for storing variables; and circuitry for comparing the incoming read requests to the queued read requests, wherein the circuitry ignores duplicates of a first read request prior to the first read request leaving the memory for queuing outgoing read requests.
Inventors
- 👤 Gary A. Frazier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 04:37
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/52; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0833; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/161; G06F13/1626; G06F13/1631; G06F15/00; G06F15/16; G06F15/161; G06F15/76; G06F15/80; G06F15/8007
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
192 words
A computation system for minimizing duplicate read requests comprising: (a) a plurality of processing systems within said computation system; (b) a broadcast bus connecting said plurality of processing systems; (c) wherein each one of said plurality of processing systems further include: i. a memory for storing variables; ii. circuitry operable for receiving incoming read requests through said broadcast bus from another processing system of said plurality of processing systems; iii. a memory for queuing said incoming read requests, wherein said memory for queuing said incoming read requests is connected to said circuitry operable for receiving said incoming read requests; iv. a memory for queuing outgoing read requests, wherein said memory for queuing outgoing read requests is connected to said broadcast bus and said memory for storing variables; and v. circuitry for comparing said incoming read requests to said queued read requests, wherein said circuitry compares said incoming read requests to addresses stored in a memory cache to determine whether said read requests are already stored in said memory cache, and wherein said circuitry adds non-duplicate read request to said memory cache and does not add duplicate read requests to said memory cache.
Claim 2
Dependent Claim
192 words
A computation system for minimizing duplicate read requests comprising: (a) a plurality of processing systems within said computation system; (b) a broadcast bus connecting said plurality of processing systems; (c) wherein each one of said plurality of processing systems further include: i. a memory for storing variables; ii. circuitry operable for receiving incoming read requests through said broadcast bus from another processing system of said plurality of processing systems; iii. a memory for queuing said incoming read requests, wherein said memory for queuing said incoming read requests is connected to said circuitry operable for receiving said incoming read requests; iv. a memory for queuing outgoing read requests, wherein said memory for queuing outgoing read requests is connected to said broadcast bus and said memory for storing variables; and v. circuitry for comparing said incoming read requests to said queued read requests, wherein said circuitry compares said incoming read requests to addresses stored in a memory cache to determine whether said read requests are already stored in said memory cache, and wherein said circuitry adds non-duplicate read request to said memory cache and does not add duplicate read requests to said memory cache.
Claim 3
Dependent Claim
17 words
The system of claim 1, wherein said memory for queuing incoming read requests is a FIFO memory.
Claim 4
Dependent Claim
17 words
The system of claim 1, wherein said memory for queuing outgoing read requests is a FIFO memory.
Claim 5
Dependent Claim
29 words
The system of claim 1, wherein said non-duplicate read requests are deleted from said memory cache after said non-duplicate read request leaves said memory for queuing outgoing read requests.
Claim 6
Dependent Claim
30 words
The system of claim 1, wherein said broadcast bus includes: a. a plurality of data lines, b. a plurality of address lines, and c. a plurality of tag field lines.
Claim 7
Dependent Claim
29 words
The system of claim 1, wherein said each of said plurality of processing systems further include a plurality of processor modules connected to each other by a backplane bus.
Claim 8
Dependent Claim
61 words
The system of claim 1, wherein each one of said plurality of processing systems further include: a. a global memory; b. a memory watcher cache connected to said global memory; c. a controller connected to said global memory and said memory watcher cache; and d. an arithmetic logic unit connected to said controller, said global memory and said memory watcher cache.
Claim 9
Dependent Claim
28 words
The system of claim 7, wherein said controller manages bus protocols used to arbitrate access by each one of said plurality of processing systems to said broadcast bus.
Claim 10
Dependent Claim
16 words
The system of claim 7, wherein said arithmetic logic unit performs arithmetic on said global memory.
Claim 11
Dependent Claim
203 words
A computation system for minimizing duplicate read requests comprising: a. a plurality of processing systems; b. a broadcast bus connecting said processing systems; c. wherein each one of said plurality of processing systems further include: i. circuitry operable for receiving incoming read requests through said broadcast bus from another processing system of said plurality of processing systems; ii. a memory for queuing incoming read requests, wherein said memory for queuing said incoming read requests is connected to said circuitry operable for receiving said incoming read requests, wherein said memory for queuing incoming read requests is a FIFO memory; iii. a memory for queuing outgoing read requests, wherein said memory for queuing outgoing read requests is connected to said broadcast bus and said memory for storing variables, wherein said memory for queuing outgoing read requests is a FIFO memory; and iv. circuitry for comparing said incoming read requests to said queued read requests, wherein said circuitry compares said incoming read requests to addresses stored in a memory cache to determine whether said read requests are already stored in said memory cache, and wherein said circuitry adds non-duplicate read request to said memory cache and does not add duplicate read requests to said memory cache.
Claim 12
Dependent Claim
203 words
A computation system for minimizing duplicate read requests comprising: a. a plurality of processing systems; b. a broadcast bus connecting said processing systems; c. wherein each one of said plurality of processing systems further include: i. circuitry operable for receiving incoming read requests through said broadcast bus from another processing system of said plurality of processing systems; ii. a memory for queuing incoming read requests, wherein said memory for queuing said incoming read requests is connected to said circuitry operable for receiving said incoming read requests, wherein said memory for queuing incoming read requests is a FIFO memory; iii. a memory for queuing outgoing read requests, wherein said memory for queuing outgoing read requests is connected to said broadcast bus and said memory for storing variables, wherein said memory for queuing outgoing read requests is a FIFO memory; and iv. circuitry for comparing said incoming read requests to said queued read requests, wherein said circuitry compares said incoming read requests to addresses stored in a memory cache to determine whether said read requests are already stored in said memory cache, and wherein said circuitry adds non-duplicate read request to said memory cache and does not add duplicate read requests to said memory cache.
Claim 13
Dependent Claim
28 words
The system of claim 10, wherein said non-duplicate read requests are deleted from said cache after said non-duplicate read request leaves said memory for queuing outgoing read requests.
Claim 14
Dependent Claim
30 words
The system of claim 10, wherein said broadcast bus includes: a. a plurality of data lines, b. a plurality of address lines, and c. a plurality of tag field lines.
Claim 15
Dependent Claim
29 words
The system of claim 10, wherein said each of said plurality of processing systems further include a plurality of processor modules connected to each other by a backplane bus.
Claim 16
Dependent Claim
84 words
The system of claim 10, wherein each one of said plurality of processing systems further include: a. a global memory; b. a memory watcher cache connected to said global memory; c. a controller connected to said global memory and said memory watcher cache, wherein said controller manages bus protocols used to arbitrate access by each one of said plurality of processing systems to said broadcast bus; and d. an arithmetic logic unit connected to said controller, said global memory and said memory watcher cache.
Claim 17
Dependent Claim
16 words
The system of claim 14, wherein said arithmetic logic unit performs arithmetic on said global memory.
Claim 18
Dependent Claim
226 words
A computation system for minimizing duplicate read requests comprising: a. a plurality of processing systems; b. a broadcast bus connecting said processing systems; c. wherein each one of said plurality of processing systems further include: i. circuitry operable for receiving read requests through said broadcast bus from another processing system of said plurality of processing systems; ii. a memory for queuing incoming read requests, wherein said memory for queuing said incoming read requests is connected to said circuitry operable for receiving said incoming read requests, wherein said memory for queuing incoming read requests is a FIFO memory; iii. a memory for queuing outgoing read requests, wherein said memory for queuing outgoing read requests is connected to said broadcast bus and said memory for storing variables, wherein said memory for queuing outgoing read requests is a FIFO memory; and iv. circuitry for comparing said incoming read requests to said queued read requests, wherein said circuitry compares said incoming read requests to addresses stored in a memory cache to determine whether said read requests are already stored in said memory cache, and wherein said circuitry adds non-duplicate read request to said memory cache and does not add duplicate read requests to said memory cache, and wherein said non-duplicate read requests are deleted from said cache after said non-duplicate read request leaves said memory for queuing outgoing read requests.
Claim 19
Dependent Claim
226 words
A computation system for minimizing duplicate read requests comprising: a. a plurality of processing systems; b. a broadcast bus connecting said processing systems; c. wherein each one of said plurality of processing systems further include: i. circuitry operable for receiving read requests through said broadcast bus from another processing system of said plurality of processing systems; ii. a memory for queuing incoming read requests, wherein said memory for queuing said incoming read requests is connected to said circuitry operable for receiving said incoming read requests, wherein said memory for queuing incoming read requests is a FIFO memory; iii. a memory for queuing outgoing read requests, wherein said memory for queuing outgoing read requests is connected to said broadcast bus and said memory for storing variables, wherein said memory for queuing outgoing read requests is a FIFO memory; and iv. circuitry for comparing said incoming read requests to said queued read requests, wherein said circuitry compares said incoming read requests to addresses stored in a memory cache to determine whether said read requests are already stored in said memory cache, and wherein said circuitry adds non-duplicate read request to said memory cache and does not add duplicate read requests to said memory cache, and wherein said non-duplicate read requests are deleted from said cache after said non-duplicate read request leaves said memory for queuing outgoing read requests.
Claim 20
Dependent Claim
30 words
The system of claim 16, wherein said broadcast bus includes: a. a plurality of data lines, b. a plurality of address lines, and c. a plurality of tag field lines.
Claim 21
Dependent Claim
95 words
The system of claim 16, wherein each one of said plurality of processing systems further include: a. a global memory; b. a memory watcher cache connected to said global memory; c. a controller connected to said global memory and said memory watcher cache, wherein said controller manages bus protocols used to arbitrate access by each one of said plurality of processing systems to said broadcast bus; and d. an arithmetic logic unit connected to said controller, said global memory and said memory watcher cache, wherein said arithmetic logic unit performs arithmetic on said global memory.
Claim 22
Dependent Claim
29 words
The system of claim 16, wherein said each of said plurality of processing systems further include a plurality of processor modules connected to each other by a backplane bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-27 | 1997-12-27 | 1998-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-27 | 2001-12-27 | 2002-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-27 | 2005-12-27 | 2006-06-28 | $7700.00 | Window Closed / Lapsed |