US4901232A
Expired / Lapsed
US
⏱️ 0.0 years remaining
I/O controller for controlling the sequencing of execution of I/O commands and for permitting modification of I/O controller operation by a host processor
Assignee: EMC Corp
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Filing: 1987-01-09
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Granted: 1990-02-13
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Expires: 2007-01-09
Abstract
Abstract A data processing system which includes a host processor and an input/output (I/O) controller unit for controlling communication with I/O devices. The controller processor receives I/O commands from the host processor, accesses and stores control block lists of control commands associated with such I/O commands, and executes the control commands from such control block lists. The controller unit stores controller information concerning the operational capability of the controller unit and the host processor is capable of accessing such controller information and in turn can modify such operational capability if desired.
Inventors
- 👤 David M. Harrington
- 👤 John R. McDaniel
- 👤 Steve A. Caldara
- 👤 Louis A. Lemone
- 👤 Kenneth R. Andrews, Jr.
- 👤 Paul Funk
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 00:05
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/124; G06F13/126
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
338 words
A system for controlling input/output operations required by a host computer, which includes host processor means and host memory means, in communication with one or more input/output devices, said system comprising: an input/output controller unit connected to said host computer and to said one or more input/output devices for controlling said input/output operation in response to input/output commands from said host processor means, said controller unit including controller processor means and controller memory means; said host memory means being accessible to said controller unit for storing a plurality of control block lists, each control block list corresponding to one of said input/output commands and including control blocks of command information; means for transferring input/output commands from said host processor means to said controller processor means of said controller unit; said controller processor means being responsive to said input/output commands transferred thereto for successively accessing from said host memory the control block lists corresponding to said input/output commands; said controller memory means being connected to said controller processor means for storing said control block lists, each including command information, control information supplied by said host processor means, status return informatin supplied by said controller processor means, and error information concerning errors which arise during execution of the operation corresponding to said control block; said controller processor means includes means for selecting one of a plurality of different sequences of said control blocks of command information from said control block lists in accordance with a predetermined algorithm in said controller memory means; and means responsive to said selected sequence of control blocks of command information for executing the operations required by said input/output commands; said controller unit further including means for storing controller information concerning the operation of said controller unit and for transferring said controller information to said host processor means; and said host processor means being responsive to said controller information for selectively modifying said controller information so as to modify the operation of said controller unit and for transferring said modified controller information to said controller unit.
Claim 2
Independent Claim
338 words
A system for controlling input/output operations required by a host computer, which includes host processor means and host memory means, in communication with one or more input/output devices, said system comprising: an input/output controller unit connected to said host computer and to said one or more input/output devices for controlling said input/output operation in response to input/output commands from said host processor means, said controller unit including controller processor means and controller memory means; said host memory means being accessible to said controller unit for storing a plurality of control block lists, each control block list corresponding to one of said input/output commands and including control blocks of command information; means for transferring input/output commands from said host processor means to said controller processor means of said controller unit; said controller processor means being responsive to said input/output commands transferred thereto for successively accessing from said host memory the control block lists corresponding to said input/output commands; said controller memory means being connected to said controller processor means for storing said control block lists, each including command information, control information supplied by said host processor means, status return informatin supplied by said controller processor means, and error information concerning errors which arise during execution of the operation corresponding to said control block; said controller processor means includes means for selecting one of a plurality of different sequences of said control blocks of command information from said control block lists in accordance with a predetermined algorithm in said controller memory means; and means responsive to said selected sequence of control blocks of command information for executing the operations required by said input/output commands; said controller unit further including means for storing controller information concerning the operation of said controller unit and for transferring said controller information to said host processor means; and said host processor means being responsive to said controller information for selectively modifying said controller information so as to modify the operation of said controller unit and for transferring said modified controller information to said controller unit.
Claim 3
Dependent Claim
53 words
A system in accordance with claim 1 wherein said controller information is stored in controller memory means in said controller unit in the form of one or more controller information blocks containing said controller information, said host processor accessing said one or more controller information blocks to selectively modify the controller information therein.
Claim 4
Dependent Claim
54 words
A system in accordance with claim 2 wherein a first controller information block contains controller information for controlling the retrying of errors which are in said controller unit or in the error code used by said controller unit during the execution of an input/output command, said host processor modifying such controller information, if desired.
Claim 5
Dependent Claim
55 words
A system in accordance with claim 3 wherein a second controller information block contains controller information concerning the input/output devices with respect to which data can be transferred by said controller unit and the manner in which said controller unit will handle such data transfers, said controller information not being modified by said host processor.
Claim 6
Dependent Claim
83 words
A system in accordance with claim 1 wherein said controller processor means is responsive to operations being executed with respect to an input/output device for providing status information concerning the status of the control block being executed currently by said controller processor means, the status of errors in the execution of said control block, and the address of the input/output device with respect to while said execution is occurring, said status information being transferred from said controller unit to said host processor means.
Claim 7
Dependent Claim
28 words
A system in accordance with claim 5 wherein said controller unit further includes status storage means for storing said status information being transferred to said host processor means.
Claim 8
Dependent Claim
73 words
A system in accordance with claim 5 wherein said controller memory means further includes one or more extended status information blocks corresponding to each input/output device with which said controller unit is in communication, each said extended status block containing additional error information required by said host processor means when an error condition cannot be resolved by said controller unit using normal error correction operation for resolution thereof by said host processor means.
Claim 9
Dependent Claim
77 words
A system in accordance with claim 1 wherein said control information includes address information concerning the location in said host main memory and in said input/output device of information being transferred between said host computer and said input/output device, the identity of said input/output device, the amount of said information, the operation to be performed with respect to said input/output device and the address of the next successive control block, if any, of said control block list.
Claim 10
Dependent Claim
48 words
A system in accordance with claim 1 wherein said error information includes information concerning the number of execution retries performed by said controller unit with respect to an error arising during operation, the type of error so arising, and the location of said error in said input/output device.
Claim 11
Dependent Claim
46 words
A system in accordance with claim 1 wherein said controller unit includes command storage means for storing input/output commands transferred from said host processor means, said command storage means includes information which identifies the command required to be executed and the argument related to such command.
Claim 12
Dependent Claim
69 words
A system in accordance with claim 1 wherein said status storage means in said controller unit includes information concerning interrupts for the host processor means with respect to errors arising during the execution of an input/output command, the type of interrupt involved, the execution status of the input/output command, a specified interrupt code if a synchronous interrupt occurs, and the input/output command operating code if a synchronous interrupt occurs.
Claim 13
Dependent Claim
46 words
A system in accordance with claim 1 and further including means for transferring a start signal from said host processor to said controller unit, said controller processor means being responsive to said start signal to begin the execution of an input/output command by said controller unit.
Claim 14
Dependent Claim
39 words
A system in accordance with claim 12 and further including means for setting and transferring a busy flag signal from said controller unit to said host processor for indicating that said controller unit is executing an input/output command operation.
Claim 15
Dependent Claim
42 words
A system in accordance with claim 13 and further including means for setting and transferring a done flag signal from said controller unit to said host processor for indicating that said controller unit has completed the execution of an input/output command operation.
Claim 16
Dependent Claim
68 words
A system in accordance with claim 14 and further including means for transferring an interrupt set flag signal from said host processor to said controller unit if said busy flag is not set and said done flag is set and means for setting and transferring an interrupt flag signal from said controller unit to said host processor in accordance thereto for indicating the setting of an interrupt condition.
Claim 17
Dependent Claim
41 words
A system in accordance with claim 15 and further including means for transferring a reset signal from said host processor to said controller unit for resetting components of said controller unit and for clearing said busy, done and interrupt flag signals.
References Cited (Backward Citations)
US3728693A
Cited
US4006466A
Cited
US4075691A
Cited
US4156932A
Cited
US4204206A
Cited
US4266271A
Cited
US4417304A
Cited
US4783739A
Cited
US4426679A
Cited
US4451884A
Cited
US4583165A
Cited
US4488258A
Cited
US4543626A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-12 | 1993-08-14 | 1994-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-12 | 1997-08-14 | 1998-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-12 | 2001-08-14 | 2002-02-13 | $7700.00 | Window Closed / Lapsed |