US5603055A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Single shared ROM for storing keyboard microcontroller code portion and CPU code portion and disabling access to a portion while accessing to the other
Assignee: NXP BV
•
Filing: 1994-01-27
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Granted: 1997-02-11
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Expires: 2014-01-27
Abstract
Abstract A shared keyboard and system ROM uses a single ROM for both the keyboard and the system operating system information (BIOS). The shared ROM is never simultaneously used for both of these functions. At initial boot-up, the system processor executes from the shared ROM to copy the system BIOS information to the system Random Access Memory DRAM. Once this copying has been completed, the shared ROM then is used by the keyboard subsystem. Different address ranges are employed in the shared ROM for the keyboard information and for the system BIOS.
Inventors
- 👤 David R. Evoy
- 👤 Lawrence D. Gould
- 👤 James R. Edwards
- 👤 Donald G. Scharnberg
- 👤 Doyne L. Metz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 09:53
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/44; G06F9/4401; G06F9/4403; G06F12/00; G06F12/02; G06F12/06; G06F12/0638
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
168 words
A method for operating a computer system using a single shared ROM memory for dissimilar processor types including a keyboard microcontroller and a host operating CPU comprising the steps of: configuring a single ROM memory into two portions, the first portion dedicated to storing keyboard microcontroller code information and the second portion dedicated to storing operating CPU code (BIOS); disabling access to the first portion of said ROM at initial boot-up of the computer, and enabling access to the second portion of said ROM at initial boot-up of the system; transferring the operating system information in the second portion of said ROM to a system random access memory (RAM) for subsequent use by the computer system; and upon completion of transfer of the operating system information from the second portion of the shared ROM to the system random access memory, disabling access to the second portion of said ROM and enabling access to the first portion of said ROM for subsequent execution and use by the keyboard microcontroller.
Claim 2
Independent Claim
168 words
A method for operating a computer system using a single shared ROM memory for dissimilar processor types including a keyboard microcontroller and a host operating CPU comprising the steps of: configuring a single ROM memory into two portions, the first portion dedicated to storing keyboard microcontroller code information and the second portion dedicated to storing operating CPU code (BIOS); disabling access to the first portion of said ROM at initial boot-up of the computer, and enabling access to the second portion of said ROM at initial boot-up of the system; transferring the operating system information in the second portion of said ROM to a system random access memory (RAM) for subsequent use by the computer system; and upon completion of transfer of the operating system information from the second portion of the shared ROM to the system random access memory, disabling access to the second portion of said ROM and enabling access to the first portion of said ROM for subsequent execution and use by the keyboard microcontroller.
Claim 3
Dependent Claim
49 words
The method according to claim 1 wherein the step of disabling access to the first portion of said ROM and enabling access to the second portion of said ROM at initial boot-up of the system is effected in response to a main system reset signal generated at initial boot-up.
Claim 4
Dependent Claim
199 words
A computer system including in combination: a system controller; a peripheral controller; a multiplex bus for transferring address and data information between said system controller and said peripheral controller; a system Random Access Memory (RAM) coupled with said system controller; a shared Read Only Memory (ROM) coupled with said peripheral controller for storing keyboard microcontroller code information in a first portion and operating CPU code (BIOS) in a second portion; a main system reset signal source coupled with said system controller and said peripheral controller for supplying a reset signal to both of said controllers; said peripheral controller responsive to said reset signal for disabling access to the first portion of said shared ROM and for enabling addressing of the second portion of said shared ROM to supply the BIOS information through said bus and said system controller to said system RAM to configure said system RAM; and logic means in said peripheral controller responsive to completion of transfer of the BIOS information from said shared ROM to said DRAM for disabling access to said second portion of said ROM and enabling access to said first portion of said ROM for subsequent execution and use by said peripheral controller.
Claim 5
Dependent Claim
199 words
A computer system including in combination: a system controller; a peripheral controller; a multiplex bus for transferring address and data information between said system controller and said peripheral controller; a system Random Access Memory (RAM) coupled with said system controller; a shared Read Only Memory (ROM) coupled with said peripheral controller for storing keyboard microcontroller code information in a first portion and operating CPU code (BIOS) in a second portion; a main system reset signal source coupled with said system controller and said peripheral controller for supplying a reset signal to both of said controllers; said peripheral controller responsive to said reset signal for disabling access to the first portion of said shared ROM and for enabling addressing of the second portion of said shared ROM to supply the BIOS information through said bus and said system controller to said system RAM to configure said system RAM; and logic means in said peripheral controller responsive to completion of transfer of the BIOS information from said shared ROM to said DRAM for disabling access to said second portion of said ROM and enabling access to said first portion of said ROM for subsequent execution and use by said peripheral controller.
Claim 6
Dependent Claim
22 words
The combination according to claim 3 wherein said first and second portions of said shared ROM comprise first and second address ranges.
Claim 7
Dependent Claim
35 words
The combination according to claim 4 wherein said first address range comprises a predetermined number of the lowest addresses for said ROM, and said second address range comprises addresses above said predetermined number of addresses.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-11 | 2000-08-12 | 2001-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-11 | 2004-08-12 | 2005-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-11 | 2008-08-12 | 2009-02-11 | $7700.00 | Window Closed / Lapsed |