Patent US5600280A successfully refreshed from Google Patents.
US5600280A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Differential amplifier and variable delay stage for use in a voltage controlled oscillator
Assignee: Cirrus Logic Inc
•
Filing: 1995-03-13
•
Granted: 1997-02-04
•
Expires: 2015-03-13
Abstract
Abstract A differential amplifier or delay cell for use in a voltage controlled oscillator comprises a pair of clipper transistors coupled across the output nodes of the amplifier for limiting the voltage swing of the output to a transistor threshold and improving the frequency response of the amplifier. A cross-coupled pair of transistors are included to provide a hysteresis response further improving the noise immunity of the amplifier. A variable control voltage is converted to a current and used to control the frequency of the output signal. An oscillator is formed from three stages, cascaded together, each stage comprising the improved differential amplifier and controlled by a differential reference signal.
Inventors
- 👤 Zhong-Xuan Zhang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 08:14
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/023; H03K3/0231; H03B; H03B5/00; H03B5/20; H03B5/24
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
443 words
A multistage voltage controlled oscillator for selectively generating a frequency variable clock signal comprising: a. a plurality of circularly cascade-coupled differential amplifier stages, each of the plurality having a differential input and a differential output; b. a differential control signal coupled to each of the plurality of amplifier stages for controlling the frequency of the clock signal; and c. means for generating the differential control signal from a single ended control voltage having: i. a first means for generating a first bias voltage responsive to the single ended control voltage; ii. a second means for generating a second bias voltage responsive to the single ended control voltage; iii. a first p-type transistor having a first gate, a first source and a first drain, wherein the first gate is coupled to the first bias voltage and the first source is coupled to a first power supply voltage; iv. a second p-type transistor having a second gate, a second source and a second drain, wherein the second gate is coupled to the second bias voltage and the second source is coupled to the first drain; v. a third p-type transistor having a third gate, a third source and a third drain, wherein the third gate is coupled to the first bias voltage and the third source is coupled to the first power supply voltage; vi. a fourth p-type transistor having a fourth gate, a fourth source and a fourth drain, wherein the fourth gate is coupled to the second bias voltage, and the fourth source is coupled to the third drain; vii. a fifth n-type transistor having a fifth gate, a fifth source and a fifth drain, wherein the fifth gate is coupled to the fifth drain, the fourth drain and a first end of the differential control signal, the fifth drain is coupled to the fourth drain and the first end of the differential control signal, and the fifth source is coupled to a second power supply voltage; viii. a sixth n-type transistor having a sixth gate, a sixth source and a sixth drain, wherein the sixth gate is coupled to the fifth gate, the fourth drain and the first end of the differential control signal, the sixth drain is coupled to the second drain and a second end of the differential control signal; and ix. a seventh n-type transistor having a seventh gate, a seventh source and a seventh drain, wherein the seventh gate is coupled to the second drain, the sixth drain, and the second end of the differential control signal, the seventh drain is coupled to the sixth source, and the seventh source is coupled to the second power supply voltage.
Claim 2
Dependent Claim
443 words
A multistage voltage controlled oscillator for selectively generating a frequency variable clock signal comprising: a. a plurality of circularly cascade-coupled differential amplifier stages, each of the plurality having a differential input and a differential output; b. a differential control signal coupled to each of the plurality of amplifier stages for controlling the frequency of the clock signal; and c. means for generating the differential control signal from a single ended control voltage having: i. a first means for generating a first bias voltage responsive to the single ended control voltage; ii. a second means for generating a second bias voltage responsive to the single ended control voltage; iii. a first p-type transistor having a first gate, a first source and a first drain, wherein the first gate is coupled to the first bias voltage and the first source is coupled to a first power supply voltage; iv. a second p-type transistor having a second gate, a second source and a second drain, wherein the second gate is coupled to the second bias voltage and the second source is coupled to the first drain; v. a third p-type transistor having a third gate, a third source and a third drain, wherein the third gate is coupled to the first bias voltage and the third source is coupled to the first power supply voltage; vi. a fourth p-type transistor having a fourth gate, a fourth source and a fourth drain, wherein the fourth gate is coupled to the second bias voltage, and the fourth source is coupled to the third drain; vii. a fifth n-type transistor having a fifth gate, a fifth source and a fifth drain, wherein the fifth gate is coupled to the fifth drain, the fourth drain and a first end of the differential control signal, the fifth drain is coupled to the fourth drain and the first end of the differential control signal, and the fifth source is coupled to a second power supply voltage; viii. a sixth n-type transistor having a sixth gate, a sixth source and a sixth drain, wherein the sixth gate is coupled to the fifth gate, the fourth drain and the first end of the differential control signal, the sixth drain is coupled to the second drain and a second end of the differential control signal; and ix. a seventh n-type transistor having a seventh gate, a seventh source and a seventh drain, wherein the seventh gate is coupled to the second drain, the sixth drain, and the second end of the differential control signal, the seventh drain is coupled to the sixth source, and the seventh source is coupled to the second power supply voltage.
Claim 3
Dependent Claim
78 words
The multistage voltage controlled oscillator as claimed in claim 1 wherein the plurality of cascade-coupled differential amplifier stages comprises a first, second and third stage, wherein the differential output of the first stage is coupled to the differential input of the second stage, the differential output of the second stage is coupled to the differential input of the third stage and the differential output of the third stage is coupled to the differential input of the first stage.
Claim 4
Dependent Claim
26 words
The multistage voltage controlled oscillator as claimed in claim 2 wherein the frequency variable clock signal is generated from the differential output of the third stage.
Claim 5
Dependent Claim
402 words
A differential amplifier and control circuit coupled between a first power supply voltage and a second power supply voltage and further coupled to receive a differential input signal, comprising: a. a differential amplifier having: i. a first transistor having a first gate, a first source and a first drain, wherein the first gate is coupled to the differential input signal; ii. a second transistor having a second gate, a second source and a second drain, wherein the second gate is coupled to the differential input signal and the second source is coupled to the first source; iii. a third transistor having a third gate, a third source and a third drain, wherein the third gate is coupled to the third drain and to the first drain and the third source is coupled to the second drain; iv. a fourth transistor having a fourth gate, a fourth source and a fourth drain, wherein the fourth gate is coupled to the fourth drain, to the second drain and to the third source and the fourth source is coupled to the first drain, the third drain and the third gate wherein a differential output signal is measured between a first output node formed at the fourth drain and a second output node formed at the fourth source, thereby automatically limiting a substantially symmetrical swing of the differential output signal; v. a fifth transistor having a fifth gate, a fifth source and a fifth drain, wherein the fifth gate is coupled to the second drain, the third source, the fourth gate and the fourth drain, the fifth drain is coupled to the first drain, the third gate, the third drain and the fourth source and the fifth source is coupled to the first power supply voltage; and vi. a sixth transistor having a sixth gate, a sixth source and a sixth drain, wherein the sixth gate is coupled to the first drain, the third gate, the third drain, the fourth source and the fifth drain, the sixth drain is coupled to the second drain, the third source, the fourth gate, and the fourth drain and the sixth source is coupled to the fifth source and the first power supply voltage; and b. means for generating a control current coupled to a control signal, the first source, the second source and the second power supply voltage for controlling a time of formation of the differential output signal.
Claim 6
Dependent Claim
402 words
A differential amplifier and control circuit coupled between a first power supply voltage and a second power supply voltage and further coupled to receive a differential input signal, comprising: a. a differential amplifier having: i. a first transistor having a first gate, a first source and a first drain, wherein the first gate is coupled to the differential input signal; ii. a second transistor having a second gate, a second source and a second drain, wherein the second gate is coupled to the differential input signal and the second source is coupled to the first source; iii. a third transistor having a third gate, a third source and a third drain, wherein the third gate is coupled to the third drain and to the first drain and the third source is coupled to the second drain; iv. a fourth transistor having a fourth gate, a fourth source and a fourth drain, wherein the fourth gate is coupled to the fourth drain, to the second drain and to the third source and the fourth source is coupled to the first drain, the third drain and the third gate wherein a differential output signal is measured between a first output node formed at the fourth drain and a second output node formed at the fourth source, thereby automatically limiting a substantially symmetrical swing of the differential output signal; v. a fifth transistor having a fifth gate, a fifth source and a fifth drain, wherein the fifth gate is coupled to the second drain, the third source, the fourth gate and the fourth drain, the fifth drain is coupled to the first drain, the third gate, the third drain and the fourth source and the fifth source is coupled to the first power supply voltage; and vi. a sixth transistor having a sixth gate, a sixth source and a sixth drain, wherein the sixth gate is coupled to the first drain, the third gate, the third drain, the fourth source and the fifth drain, the sixth drain is coupled to the second drain, the third source, the fourth gate, and the fourth drain and the sixth source is coupled to the fifth source and the first power supply voltage; and b. means for generating a control current coupled to a control signal, the first source, the second source and the second power supply voltage for controlling a time of formation of the differential output signal.
Claim 7
Dependent Claim
37 words
The differential amplifier as claimed in claim 4 wherein the means for generating a control current comprises a variable current source for controlling the frequency response of a differential output signal in response to the control signal.
Claim 8
Dependent Claim
116 words
The differential amplifier as claimed in claim 5 wherein the differential amplifier comprises a first stage of an oscillator and wherein the oscillator further comprises a second stage and a third stage, each identical to the first stage and each stage having a differential input and a differential output, and further wherein the differential output of the first stage is coupled to the differential input of the second stage, the differential output of the second stage is coupled to the differential input of the third stage and the differential output of the third stage is coupled to the differential input of the first stage and further wherein the control signal is common to all three stages.
Claim 9
Dependent Claim
60 words
The multistage voltage controlled oscillator as claimed in claim 1 wherein the plurality of cascade-coupled differential amplifier stages comprises a first and second stage, wherein the differential output of the first stage is coupled to the differential input of the second stage and the differential output of the second stage is coupled to the differential input of the first stage.
Claim 10
Dependent Claim
26 words
The multistage voltage controlled oscillator as claimed in claim 7 wherein the frequency variable clock signal is generated from the differential output of the second stage.
Claim 11
Dependent Claim
89 words
The differential amplifier as claimed in claim 5 wherein the differential amplifier comprises a first stage of an oscillator and wherein the oscillator further comprises a second stage identical to the first stage having a differential input and a differential output, and further wherein the differential output of the first stage is coupled to the differential input of the second stage, the differential output of the second stage is coupled to the differential input of the first stage and further wherein the control signal is common to both stages.
Claim 12
Dependent Claim
118 words
The differential amplifier as claimed in claim 5 wherein the variable current source comprises: a. a seventh transistor having a seventh gate, a seventh source and a seventh drain, wherein the seventh gate is coupled to a first end of a differential control signal responsive to the control signal, the seventh drain is coupled to the first source and the second source; b. an eighth transistor having an eighth gate, an eighth source and an eighth drain, wherein the eighth gate is coupled to a second end of a differential control signal responsive to the control signal, the eighth drain is coupled to the seventh source, and the eighth source is coupled to the second power supply voltage.
Claim 13
Dependent Claim
384 words
The differential amplifier as claimed in claim 10 wherein the variable current source further comprises a means for generating the differential control signal from the control having: a. a first means for generating a first bias voltage responsive to the control signal; b. a second means for generating a second bias voltage responsive to the control signal; c. a ninth transistor having a ninth gate, a ninth source and a ninth drain, wherein the ninth gate is coupled to the first bias voltage and the ninth source is coupled to the first power supply voltage; d. a tenth transistor having a tenth gate, a tenth source and a tenth drain, wherein the tenth gate is coupled to the second bias voltage and the tenth source is coupled to the ninth drain; e. an eleventh transistor having an eleventh gate, an eleventh source and an eleventh drain, wherein the eleventh gate is coupled to the first bias voltage and the eleventh source is coupled to the first power supply voltage; f. a twelfth transistor having a twelfth gate, a twelfth source and a twelfth drain, wherein the twelfth gate is coupled to the second bias voltage, and the twelfth source is coupled to the eleventh drain; g. a thirteenth transistor having a thirteenth gate, a thirteenth source and a thirteenth drain, wherein the thirteenth gate is coupled to the thirteenth and twelfth drains and a first end of the differential control signal, the thirteenth drain is coupled to the twelfth drain and the first end of the differential control signal, and the thirteenth source is coupled to the second power supply voltage; h. a fourteenth transistor having a fourteenth gate, a fourteenth source and a fourteenth drain, wherein the fourteenth gate is coupled to the thirteenth gate, twelfth drain and the first end of the differential control signal, the fourteenth drain is coupled to the tenth source and a second end of the differential control signal; and i. a fifteenth transistor having a fifteenth gate, a fifteenth source and a fifteenth drain, wherein the fifteenth gate is coupled to the tenth drain, the fourteenth drain, and the second end of the differential control signal, the fifteenth drain is coupled to the fourteenth source, and the fifteenth source is coupled to the second power supply voltage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-04 | 2000-08-05 | 2001-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-04 | 2004-08-05 | 2005-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-04 | 2008-08-05 | 2009-02-04 | $7700.00 | Window Closed / Lapsed |