Patent US5600153A successfully refreshed from Google Patents.
US5600153A
Expired / Lapsed
US
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Conductive polysilicon lines and thin film transistors
Assignee: Micron Technology Inc
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Filing: 1995-05-26
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Granted: 1997-02-04
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Expires: 2015-05-26
Abstract
Abstract A semiconductor processing method of forming a conductive polysilicon line relative to a substrate includes, a) providing a line of silicon on a substrate, the line having an outer top surface and outwardly exposed opposing outer sidewall surfaces, the line ultimately comprising conductively doped polysilicon; b) masking the line outer top surface with a masking material; c) with the masking material in place, depositing a metal layer atop the substrate and over the masking material and the outwardly exposed line outer sidewall surfaces; d) annealing the line to impart a silicidation reaction between the metal and opposing silicon sidewalls to form opposing metal silicide runners extending along the line sidewalls, the masking material preventing a silicidation reaction from occurring between the metal and line outer top surface; and e) stripping the metal layer from atop the line. Such a line is preferably used as a bottom gate for a thin film transistor. The invention also includes conductive polysilicon lines and thin film transistors.
Inventors
- 👤 Monte Manning
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 08:29
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0316; H10D30/0321; H10D30/60; H10D30/67; H10D30/6729; H10D30/6737; H10D30/6739; H10D64/00; H10D64/01; H10D64/013
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
107 words
A bottom gated thin film transistor comprising: a substrate; a conductively doped polysilicon bottom gate line lying atop the substrate, the bottom gate line having an outer top gating surface and opposing outer sidewalls; a gate dielectric layer lying atop the bottom gate outer top gating surface; a thin film transistor layer lying atop the gate dielectric layer, the thin film transistor layer comprising a source region, a drain region, and a channel region lying intermediate the source region and the drain region; and the bottom gate line sidewalls comprising a conductivity enhancing metal silicide covering a predominant portion of the sidewalls and running along the line.
Claim 2
Dependent Claim
107 words
A bottom gated thin film transistor comprising: a substrate; a conductively doped polysilicon bottom gate line lying atop the substrate, the bottom gate line having an outer top gating surface and opposing outer sidewalls; a gate dielectric layer lying atop the bottom gate outer top gating surface; a thin film transistor layer lying atop the gate dielectric layer, the thin film transistor layer comprising a source region, a drain region, and a channel region lying intermediate the source region and the drain region; and the bottom gate line sidewalls comprising a conductivity enhancing metal silicide covering a predominant portion of the sidewalls and running along the line.
Claim 3
Dependent Claim
40 words
The bottom gated thin film transistor of claim 1 wherein the entirety of the sidewalls are covered by the metal silicide from where the line joins with the substrate to where the respective sidewalls join with the outer top surface.
Claim 4
Dependent Claim
25 words
The bottom gated thin film transistor of claim 1 wherein a predominant portion of the outer top gating surface does not comprise a metal silicide.
Claim 5
Dependent Claim
56 words
The bottom gated thin film transistor of claim 1 wherein, the entirety of the sidewalls are covered by the metal silicide from where the line joins with the substrate to where the respective sidewalls join with the outer top surface; and a predominant portion of the outer top gating surface does not comprise a metal silicide.
Claim 6
Dependent Claim
32 words
The bottom gated thin film transistor of claim 1 further comprising insulating spacers provided over the metal silicide, the gate dielectric layer and thin film layer being provided over the insulating spacers.
Claim 7
Dependent Claim
64 words
The bottom gated thin film transistor of claim 1 further comprising insulating spacers provided over the metal silicide, the gate dielectric layer and thin film layer being provided over the insulating spacers; and wherein the entirety of the sidewalls are covered by the metal silicide from where the line joins with the substrate to where the respective sidewalls join with the outer top surface.
Claim 8
Dependent Claim
49 words
The bottom gated thin film transistor of claim 1 further comprising insulating spacers provided over the metal silicide, the gate dielectric layer and thin film layer being provided over the insulating spacers; and wherein a predominant portion of the outer top gating surface does not comprise a metal silicide.
Claim 9
Dependent Claim
80 words
The bottom gated thin film transistor of claim 1 further comprising insulating spacers provided over the metal silicide, the gate dielectric layer and thin film layer being provided over the insulating spacers; and wherein the entirety of the sidewalls are covered by the metal silicide from where the line joins with the substrate to where the respective sidewalls join with the outer top surface; and a predominant portion of the outer top gating surface does not comprise a metal silicide.
Claim 10
Dependent Claim
108 words
A bottom gated thin film transistor comprising: a substrate; a conductively doped polysilicon bottom gate line lying atop the substrate, the bottom gate line having an outer top gating surface and opposing outer sidewalls; a gate dielectric layer lying atop the bottom gate outer top gating surface; a thin film transistor layer lying atop the gate dielectric layer, the thin film transistor layer comprising a source region, a drain region, and a channel region lying intermediate the source region and the drain region; and at least one of the sidewalls comprising a conductivity enhancing metal silicide covering a predominant portion of the sidewall and running along the line.
Claim 11
Dependent Claim
108 words
A bottom gated thin film transistor comprising: a substrate; a conductively doped polysilicon bottom gate line lying atop the substrate, the bottom gate line having an outer top gating surface and opposing outer sidewalls; a gate dielectric layer lying atop the bottom gate outer top gating surface; a thin film transistor layer lying atop the gate dielectric layer, the thin film transistor layer comprising a source region, a drain region, and a channel region lying intermediate the source region and the drain region; and at least one of the sidewalls comprising a conductivity enhancing metal silicide covering a predominant portion of the sidewall and running along the line.
Claim 12
Dependent Claim
45 words
The bottom gated thin film transistor of claim 9, wherein the entirety of the at least one sidewall is covered by the metal silicide from where the line joins with the substrate to where the at least one sidewall joins with the outer top surface.
Claim 13
Dependent Claim
25 words
The bottom gated thin film transistor of claim 9, wherein a predominant portion of the outer top gating surface does not comprise a metal silicide.
Claim 14
Dependent Claim
33 words
The bottom gated thin film transistor of claim 9 further comprising an insulating spacer provided over the metal silicide, the gate dielectric layer and thin film layer being provided over the insulating spacer.
Claim 15
Dependent Claim
103 words
A thin film transistor comprising: a substrate; a conductively doped semiconductive material thin film transistor gate line over the substrate, the line having a gating surface and opposing outer sidewalls, wherein a predominant portion of the gating surface does not comprise a metal silicide; at least one of the sidewalls comprising a conductivity enhancing metal silicide covering a predominant portion of the sidewall and running along the line; and a thin film layer of semiconductive material over the substrate and operably adjacent the thin film transistor gate line, the thin film layer comprising a channel region operably adjacent the thin film gating surface.
Claim 16
Dependent Claim
103 words
A thin film transistor comprising: a substrate; a conductively doped semiconductive material thin film transistor gate line over the substrate, the line having a gating surface and opposing outer sidewalls, wherein a predominant portion of the gating surface does not comprise a metal silicide; at least one of the sidewalls comprising a conductivity enhancing metal silicide covering a predominant portion of the sidewall and running along the line; and a thin film layer of semiconductive material over the substrate and operably adjacent the thin film transistor gate line, the thin film layer comprising a channel region operably adjacent the thin film gating surface.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-04 | 2000-08-05 | 2001-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-04 | 2004-08-05 | 2005-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-04 | 2008-08-05 | 2009-02-04 | $7700.00 | Window Closed / Lapsed |