US4880753A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating a polysilicon thin film transistor
Assignee: The General Electric Company PLC
•
Filing: 1989-02-16
•
Granted: 1989-11-14
•
Expires: 2009-02-16
Abstract
Abstract In a process for manufacturing a thin film transistor, a first polysilicon layer is formed on a substrate and a silicon dioxide layer is formed on a region of the first polysilicon layer leaving exposed regions of that layer. A second polysilicon layer is formed on the silicon dioxide layer and aligned therewith. Regions of a selectively-grown electrically-conductive film are deposited on the second polysilicon layer and on the exposed regions of the first polysilicon layer, the film being such that it wil not grow on the edges of the silicon dioxide layer, but will grow on the exposed polysilicon to form gate, source and drain electrodes. The edges of the silicon dioxide layer therefore remain uncoated. The film may be formed of tungsten or may be formed, for example, by selective silicon epitaxy, phosphorus doped.
Inventors
- 👤 Douglas B. Meakin
- 👤 Piero Migliorato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:20
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0321; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6729; H10D30/6737; H10D30/6739; Y; Y10; Y10S; Y10S148/00; Y10S148/147
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
114 words
A process for manufacturing a thin film transistor, including the steps of forming a first polysilicon layer on a substrate; forming a silicon dioxide layer on a region of said first polysilicon layer leaving exposed regions of said first polysilicon layer; forming a second polysilicon layer on said silicon dioxide layer and aligned therewith; and depositing on said second polysilicon layer and on said exposed regions of said first polysilicon layer, regions of a selectively-grown electrically-conductive film, which film will not grow on the edges of said silicon dioxide layer but will grow on said exposed polysilicon, said selectively-grown regions acting as source and drain regions and gate electrode of the thin film transistor.
Claim 2
Dependent Claim
114 words
A process for manufacturing a thin film transistor, including the steps of forming a first polysilicon layer on a substrate; forming a silicon dioxide layer on a region of said first polysilicon layer leaving exposed regions of said first polysilicon layer; forming a second polysilicon layer on said silicon dioxide layer and aligned therewith; and depositing on said second polysilicon layer and on said exposed regions of said first polysilicon layer, regions of a selectively-grown electrically-conductive film, which film will not grow on the edges of said silicon dioxide layer but will grow on said exposed polysilicon, said selectively-grown regions acting as source and drain regions and gate electrode of the thin film transistor.
Claim 3
Dependent Claim
16 words
A process as claimed in claim 1, wherein said electrically-conductive film is a layer of tungsten.
Claim 4
Dependent Claim
31 words
A process as claimed in claim 2, wherein said deposition step comprises introducing tungsten hexafluoride gas into an evacuated chamber containing the substrate with the polysilicon and silicon dioxide layers thereon.
Claim 5
Dependent Claim
27 words
A process as claimed in claim 3, wherein during said deposition step the temperature of said substrate is maintained in the range of 350° to 450° C.
Claim 6
Dependent Claim
47 words
A process as claimed in claim 1, wherein after deposition of the film, the substrate with said layers and said film thereon is heated to cause diffusion of the material of the film into the regions of the first polysilicon layer and into the second polysilicon layer.
References Cited (Backward Citations)
US4631563A
Cited
US4823180A
Cited
JPS58178562A
Cited
US4675713A
Cited
US4814842A
Cited
US4727044A
Cited
US4772927A
Cited
US4755865A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-13 | 1993-05-15 | 1993-11-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-13 | 1997-05-15 | 1997-11-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-13 | 2001-05-15 | 2001-11-14 | $7700.00 | Window Closed / Lapsed |