Method of fabricating a self-aligned high speed MOSFET device

Claim 1

A method of fabricating a field effect transistor in a surface region of a semiconductor substrate comprising the steps of a) providing a semiconductor substrate having a pad silicon oxide layer on a surface of the substrate, b) forming a silicon nitride layer over said pad silicon oxide layer, c) removing a portion of said silicon nitride layer to expose a surface region of said substrate, d) oxidizing said surface region, thereby forming an oxide layer, e) removing a portion of said oxide layer to form an opening and expose a portion of said surface region, f) implanting dopant ions through the opening in said oxide layer and forming a punchthrough stopper region spaced from said surface region, g) forming a gate dielectric on said portion of said surface region, h) depositing gate electrode material on said gate dielectric and overlying said silicon nitride layer, i) removing both said gate electrode material overlying said silicon nitride layer and said silicon nitride layer thereby leaving a gate electrode on said gate dielectric, and j) forming source and drain regions in said surface region using said gate electrode as an implantation mask for self-alignment.

Claim 2

A method of fabricating a field effect transistor in a surface region of a semiconductor substrate comprising the steps of a) providing a semiconductor substrate having a pad silicon oxide layer on a surface of the substrate, b) forming a silicon nitride layer over said pad silicon oxide layer, c) removing a portion of said silicon nitride layer to expose a surface region of said substrate, d) oxidizing said surface region, thereby forming an oxide layer, e) removing a portion of said oxide layer to form an opening and expose a portion of said surface region, f) implanting dopant ions through the opening in said oxide layer and forming a punchthrough stopper region spaced from said surface region, g) forming a gate dielectric on said portion of said surface region, h) depositing gate electrode material on said gate dielectric and overlying said silicon nitride layer, i) removing both said gate electrode material overlying said silicon nitride layer and said silicon nitride layer thereby leaving a gate electrode on said gate dielectric, and j) forming source and drain regions in said surface region using said gate electrode as an implantation mask for self-alignment.