Flash EEPROM array with floating substrate erase operation

Claim 2

A memory cell which is programmable and erasable, said memory cell comprising: a first substrate of a first type; a source region of a second type formed on said first substrate; a drain region of said second type formed on said first substrate; a channel of said first type formed on said first substrate, said channel being positioned between said source region and said drain region, wherein said source region is single-diffused so as to minimize the length of said channel; a floating gate positioned over said channel; a control gate positioned over the floating gate; and means for allowing said first substrate to float during erasure.

Claim 3

The memory cell as recited in claim 1, further comprising: a second substrate of said first type; and a deep well of said second type formed on said second substrate, said first substrate being formed on said deep well.

Claim 4

The memory cell as recited in claim 2, wherein said first type is a P-type semiconductor and said second type is a N-type semiconductor.

Claim 5

A flash EEPROM comprising: an array of programmable and erasable memory cells, the memory cells being organized in rows and columns, each of the memory cell having a first substrate of a first type, a source region of a second type formed on said first substrate, a drain region of said second type formed on said first substrate, a channel of said first type formed on said first substrate, said channel being positioned between said source region and said drain region, wherein said source region is single-diffused so as to minimize the length of said channel; a floating gate positioned over said channel, and a control gate positioned over said floating gate; a plurality of bit lines, each coupled to said drains of one of said columns of cells in said array; a plurality of word lines, each coupled to said gates of one of said rows of cells in said array; and means for allowing said first substrates to float during erasure.

Claim 6

A flash EEPROM comprising: an array of programmable and erasable memory cells, the memory cells being organized in rows and columns, each of the memory cell having a first substrate of a first type, a source region of a second type formed on said first substrate, a drain region of said second type formed on said first substrate, a channel of said first type formed on said first substrate, said channel being positioned between said source region and said drain region, wherein said source region is single-diffused so as to minimize the length of said channel; a floating gate positioned over said channel, and a control gate positioned over said floating gate; a plurality of bit lines, each coupled to said drains of one of said columns of cells in said array; a plurality of word lines, each coupled to said gates of one of said rows of cells in said array; and means for allowing said first substrates to float during erasure.

Claim 7

The flash EEPROM as recited in claim 4, further comprising: a second substrate of said first type; and a deep well of said second type formed on said second substrate, said first substrates being formed on said deep well.

Claim 8

The flash EEPROM as recited in claim 5, wherein said first type is a P-type semiconductor and said second type is a N-type semiconductor.

Claim 9

The flash EEPROM as recited in claim 4, further comprising: means for providing a first voltage to said first substrates during programming, said first voltage is in equal to or less than 0 volt.

Claim 10

The flash EEPROM as recited in claim 7, wherein: said first voltage is in the range of approximately 0 volt to -5 volts.

Claim 11

A flash EEPROM comprising: an array of programmable and erasable memory cells, the memory cells being organized in rows and columns, each of the memory cell having a first substrate of a first type, a source region of a second type formed on said first substrate, a drain region of said second type formed on said first substrate, a channel of said first type formed on said first substrate, said channel being positioned between said source region and drain region, wherein said source region is single-diffused so as to minimize the length of said channel; a floating gate positioned over said channel, and a control gate positioned over said floating gate; a plurality of bit lines, each coupled to said drains of one of said columns of cells in said array; a plurality of word lines, each coupled to said gates of one of said rows of cells in said array; and logic circuit means for providing a plurality of voltages to said memory cells for programming and erasure, said logic circuit means further comprising: a source voltage supply means for generating and supplying a first voltage to the source of each memory cell during erasure; a control gate voltage supply means for generating and supplying a second voltage to said control gate of each memory cell during erasure; and a substrate voltage supply means for allowing said first substrates to float during erasure.

Claim 12

A flash EEPROM comprising: an array of programmable and erasable memory cells, the memory cells being organized in rows and columns, each of the memory cell having a first substrate of a first type, a source region of a second type formed on said first substrate, a drain region of said second type formed on said first substrate, a channel of said first type formed on said first substrate, said channel being positioned between said source region and drain region, wherein said source region is single-diffused so as to minimize the length of said channel; a floating gate positioned over said channel, and a control gate positioned over said floating gate; a plurality of bit lines, each coupled to said drains of one of said columns of cells in said array; a plurality of word lines, each coupled to said gates of one of said rows of cells in said array; and logic circuit means for providing a plurality of voltages to said memory cells for programming and erasure, said logic circuit means further comprising: a source voltage supply means for generating and supplying a first voltage to the source of each memory cell during erasure; a control gate voltage supply means for generating and supplying a second voltage to said control gate of each memory cell during erasure; and a substrate voltage supply means for allowing said first substrates to float during erasure.

Claim 13

The flash EEPROM as recited in claim 9, further comprising: a second substrate of said first type; and a deep well of said second type formed on said second substrate, said first substrates being formed on said deep well.

Claim 14

The flash EEPROM as recited in claim 10, wherein said first type is P-type semiconductor and said second type is N-type semiconductor.

Claim 15

The flash EEPROM as recited in claim 9, wherein said first voltage is in the range of approximately +5 to +12 volts.

Claim 16

The flash EEPROM as recited in claim 12, wherein said second voltage is in the range of approximately 0 to -10 volts.

Claim 17

The flash EEPROM as recited in claim 9, wherein said substrate voltage supply means supplies a third voltage to the first substrate during programming, said third voltage is equal to or less than 0 volt.

Claim 18

The flash EEPROM as recited in claim 14, wherein: said third voltage is in the range of approximately 0 volt to -5 volts.

Claim 19

A flash EEPROM comprising: an array of programmable and erasable memory cells, the memory cells being organized in rows and columns, each of the memory cell having a P-type first substrate, a N-type source region formed on said first substrate, a N-type drain region formed on said first substrate, a P-type channel on said first substrate, said channel being positioned between said source region and said drain region, wherein said source region is single-diffused so as to minimize the length of said channel, a floating gate positioned over said channel, and a control gate positioned over said floating gate a P-type second substrate; a N-type deep well formed on said second substrate, said first substrate being formed on said deep well; a plurality of bit lines, each coupled to said drains of one of said columns of cells in said array; and a plurality of word lines, each coupled to said gates of one of said rows of cells in said array; and a logic circuit means for providing a plurality of voltages to said memory cells for programming and erasure, said logic circuit means comprises a source voltage supply means for generating and supplying a first voltage to the source of each memory cell during erasure, said first voltage is in the range of approximately +5 volts to +12 volts, a control gate voltage supply means for generating and supplying a second voltage to said control gate of each memory cell during erasure, said second voltage is in the range of approximately 0 volt to -10 volts, and a substrate voltage supply means for allowing said first substrates to float during erasure.

Claim 20

A flash EEPROM comprising: an array of programmable and erasable memory cells, the memory cells being organized in rows and columns, each of the memory cell having a P-type first substrate, a N-type source region formed on said first substrate, a N-type drain region formed on said first substrate, a P-type channel on said first substrate, said channel being positioned between said source region and said drain region, wherein said source region is single-diffused so as to minimize the length of said channel, a floating gate positioned over said channel, and a control gate positioned over said floating gate a P-type second substrate; a N-type deep well formed on said second substrate, said first substrate being formed on said deep well; a plurality of bit lines, each coupled to said drains of one of said columns of cells in said array; and a plurality of word lines, each coupled to said gates of one of said rows of cells in said array; and a logic circuit means for providing a plurality of voltages to said memory cells for programming and erasure, said logic circuit means comprises a source voltage supply means for generating and supplying a first voltage to the source of each memory cell during erasure, said first voltage is in the range of approximately +5 volts to +12 volts, a control gate voltage supply means for generating and supplying a second voltage to said control gate of each memory cell during erasure, said second voltage is in the range of approximately 0 volt to -10 volts, and a substrate voltage supply means for allowing said first substrates to float during erasure.

Claim 21

The flash EEPROM as recited in claim 16, wherein said substrate voltage supply means supplies a third voltage to the first substrate during programming, said third voltage is equal to or less than 0 volt.

Claim 22

The flash EEPROM as recited in claim 17, wherein said third voltage is in the range of approximately 0 volt to -5 volts.

Claim 23

A flash EEPROM comprising: an array of programmable and erasable memory cells, the memory cells being organized in rows and columns, each of the memory cell having: a P-type first substrate, a N-type source region formed on said first substrate, a N-type drain region formed on said first substrate, a P-type channel on said first substrate, said channel being positioned between said source region and said drain region, wherein said source region is single-diffused so as to minimize the length of said channel, a floating gate positioned over said channel, said floating gate for storing charge carriers, a control gate positioned over said floating gate, and a thin dielectric separating said floating gate from said source region such that charge careers may tunnel from said floating gate to said source region; a P-type second substrate; a N-type deep well formed on said second substrate, said first substrate being formed on said deep well; a plurality of bit lines, each coupled to said drains of one of said columns of cells in said array; and a plurality of word lines, each coupled to said gates of one of said rows of cells in said array; a common source line defined in said second substrate, said common source line coupled to said source regions; a first voltage supply means defined on said second substrate to charge said common source line to a first voltage level for inducing stored charge carriers to tunnel from said floating gates of said cells to their respective source regions during erasure; a second voltage supply means defined on said second substrate to charge said word lines to a second voltage level for further inducing stored charge carriers to tunnel from said floating gates of said cells to their respective source regions during erasure; and a substrate switching means operatively coupled to said first substrates for selectively coupling said first substrates to allow said first substrates to float during erasure and to be coupled to a voltage in the range of approximately 0 volt to -5 volts during programming.

Claim 24

A flash EEPROM comprising: an array of programmable and erasable memory cells, the memory cells being organized in rows and columns, each of the memory cell having: a P-type first substrate, a N-type source region formed on said first substrate, a N-type drain region formed on said first substrate, a P-type channel on said first substrate, said channel being positioned between said source region and said drain region, wherein said source region is single-diffused so as to minimize the length of said channel, a floating gate positioned over said channel, said floating gate for storing charge carriers, a control gate positioned over said floating gate, and a thin dielectric separating said floating gate from said source region such that charge careers may tunnel from said floating gate to said source region; a P-type second substrate; a N-type deep well formed on said second substrate, said first substrate being formed on said deep well; a plurality of bit lines, each coupled to said drains of one of said columns of cells in said array; and a plurality of word lines, each coupled to said gates of one of said rows of cells in said array; a common source line defined in said second substrate, said common source line coupled to said source regions; a first voltage supply means defined on said second substrate to charge said common source line to a first voltage level for inducing stored charge carriers to tunnel from said floating gates of said cells to their respective source regions during erasure; a second voltage supply means defined on said second substrate to charge said word lines to a second voltage level for further inducing stored charge carriers to tunnel from said floating gates of said cells to their respective source regions during erasure; and a substrate switching means operatively coupled to said first substrates for selectively coupling said first substrates to allow said first substrates to float during erasure and to be coupled to a voltage in the range of approximately 0 volt to -5 volts during programming.

Claim 25

The flash EEPROM as recited in claim 19, wherein said drain region of each cell is single-diffused so as to further minimize the length of said channel region.

Claim 26

The flash EEPROM as recited in claim 19, wherein said thin dielectric covers said channel region and is of uniform thickness over said channel region.