US5598027A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device and method of fabricating the same
Assignee: Mitsubishi Electric Corp
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Filing: 1995-12-21
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Granted: 1997-01-28
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Expires: 2015-12-21
Abstract
Abstract Disclosed herein is a semiconductor device, which can effectively prevent a lower insulating layer from formation of a recess resulting from etching during formation of a groove for connecting interconnection layers with each other. In this semiconductor device, a first etching prevention film is formed on a first interlayer insulating film, so that a second interlayer insulating film is formed on the first etching prevention film.
Inventors
- 👤 Masazumi Matsuura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 00:23
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/45; H10W20/48; H10W20/01; H10W20/071; H10W20/074; H10W20/081; H10W20/084; H10W20/088; H10W20/41; H10W20/42
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
142 words
A semiconductor device having a multilayer interconnection structure, comprising: a first insulating layer having a first opening, the first insulating layer being formed on a semiconductor substrate; a first etching prevention film formed on said first insulating layer; a first interconnection layer formed in said first opening; a second insulating layer having a second opening, the second insulating layer being formed on said first etching prevention film and said first interconnection layer; and a second interconnection layer formed in said second opening and formed on and electrically connected with said first interconnection layer, said second interconnection layer being further formed on and in contact with an upper surface of said first etching prevention film, wherein said first etching prevention film is in direct contact with a side surface of said first interconnection layer and an upper surface of said first insulating layer.
Claim 2
Dependent Claim
142 words
A semiconductor device having a multilayer interconnection structure, comprising: a first insulating layer having a first opening, the first insulating layer being formed on a semiconductor substrate; a first etching prevention film formed on said first insulating layer; a first interconnection layer formed in said first opening; a second insulating layer having a second opening, the second insulating layer being formed on said first etching prevention film and said first interconnection layer; and a second interconnection layer formed in said second opening and formed on and electrically connected with said first interconnection layer, said second interconnection layer being further formed on and in contact with an upper surface of said first etching prevention film, wherein said first etching prevention film is in direct contact with a side surface of said first interconnection layer and an upper surface of said first insulating layer.
Claim 3
Dependent Claim
20 words
A semiconductor device in accordance with claim 1, wherein said first etching prevention film is a polyphenylsilsesquioxane film (PPSQ film).
Claim 4
Dependent Claim
39 words
A semiconductor device in accordance with claim 1, wherein said second opening includes a via hole contact opening having a first inner diameter, and an interconnection opening having a second inner diameter being larger than said first inner diameter.
Claim 5
Dependent Claim
179 words
A semiconductor device having a multilayer interconnection structure, comprising: a first insulating layer having a first opening, the first insulating layer being formed on a semiconductor substrate; a first etching prevention film formed on said first insulating layer; a first interconnection layer formed in said first opening; a second insulating layer having a second opening, the second insulating layer being formed on said first etching prevention film and said first interconnection layer; a second interconnection layer formed in said second opening and electrically connected with said first interconnection layer; a second etching prevention film formed on said second insulating layer; a third insulating layer having a third opening, the third insulating layer being formed on said second etching prevention film and said second interconnection layer, and a third interconnection layer formed in said third opening and electrically connected with said second interconnection layer, wherein said first and second etching prevention films are in direct contact with a side surface of said first and second interconnection layers, respectively, and an upper surface of said first and second insulating layer, respectively.
Claim 6
Dependent Claim
179 words
A semiconductor device having a multilayer interconnection structure, comprising: a first insulating layer having a first opening, the first insulating layer being formed on a semiconductor substrate; a first etching prevention film formed on said first insulating layer; a first interconnection layer formed in said first opening; a second insulating layer having a second opening, the second insulating layer being formed on said first etching prevention film and said first interconnection layer; a second interconnection layer formed in said second opening and electrically connected with said first interconnection layer; a second etching prevention film formed on said second insulating layer; a third insulating layer having a third opening, the third insulating layer being formed on said second etching prevention film and said second interconnection layer, and a third interconnection layer formed in said third opening and electrically connected with said second interconnection layer, wherein said first and second etching prevention films are in direct contact with a side surface of said first and second interconnection layers, respectively, and an upper surface of said first and second insulating layer, respectively.
Claim 7
Dependent Claim
20 words
A semiconductor device in accordance with claim 1, wherein the first and second insulating layers are formed of silicon dioxide.
Claim 8
Dependent Claim
31 words
A semiconductor device in accordance with claim 4, wherein said third interconnection layer is formed on said second interconnection layer and said second etching prevention film in contact with the same.
Claim 9
Dependent Claim
21 words
A semiconductor device in accordance with claim 4, wherein the first, second and third insulating layers are formed of silicon dioxide.
Claim 10
Dependent Claim
20 words
A semiconductor device in accordance with claim 4, wherein the first and second etching prevention films are formed of polyphenylsilsesquioxane.
Claim 11
Dependent Claim
25 words
The semiconductor device according to claim 1, wherein said first etching prevention film is in direct contact with side surfaces of said first interconnection layer.
Claim 12
Dependent Claim
124 words
A semiconductor device having a multilayer interconnection structure, comprising: a first insulating layer having a first opening, the first insulating layer being formed on a semiconductor substrate; a first etching prevention film formed on said first insulating layer; a first interconnection layer formed in said first opening; a second insulating layer having a second opening, the second insulating layer being formed on said first etching prevention film and on and in direct contact with an upper surface of said first interconnection layer; and a second interconnection layer formed in said second opening and formed on and electrically connected with said first interconnection layer, said second interconnection layer being further formed on and in contact with an upper surface of said first etching prevention film.
Claim 13
Dependent Claim
124 words
A semiconductor device having a multilayer interconnection structure, comprising: a first insulating layer having a first opening, the first insulating layer being formed on a semiconductor substrate; a first etching prevention film formed on said first insulating layer; a first interconnection layer formed in said first opening; a second insulating layer having a second opening, the second insulating layer being formed on said first etching prevention film and on and in direct contact with an upper surface of said first interconnection layer; and a second interconnection layer formed in said second opening and formed on and electrically connected with said first interconnection layer, said second interconnection layer being further formed on and in contact with an upper surface of said first etching prevention film.
Claim 14
Dependent Claim
153 words
A semiconductor device having a multilayer interconnection structure, comprising: a first insulating layer having a first opening, the first insulating layer being formed on a semiconductor substrate; a first etching prevention film formed on said first insulating layer; a first interconnection layer formed in said first opening; a second insulating layer having a second opening, the second insulating layer being formed on said first etching prevention film and on and in direct contact with an upper surface of said first interconnection layer; a second interconnection layer formed in said second opening and electrically connected with said first interconnection layer; a second etching prevention film formed on said second insulating layer; a third insulating layer having a third opening, the third insulating layer being formed on said second etching prevention film and said second interconnection layer, and a third interconnection layer formed in said third opening and electrically connected with said second interconnection layer.
Claim 15
Dependent Claim
153 words
A semiconductor device having a multilayer interconnection structure, comprising: a first insulating layer having a first opening, the first insulating layer being formed on a semiconductor substrate; a first etching prevention film formed on said first insulating layer; a first interconnection layer formed in said first opening; a second insulating layer having a second opening, the second insulating layer being formed on said first etching prevention film and on and in direct contact with an upper surface of said first interconnection layer; a second interconnection layer formed in said second opening and electrically connected with said first interconnection layer; a second etching prevention film formed on said second insulating layer; a third insulating layer having a third opening, the third insulating layer being formed on said second etching prevention film and said second interconnection layer, and a third interconnection layer formed in said third opening and electrically connected with said second interconnection layer.
Claim 16
Dependent Claim
30 words
The semiconductor device according to claim 4, wherein said first and second etching prevention films are formed in direct contact with side surfaces of said first and second interconnection layers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2000-01-28 | 2000-07-29 | 2001-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-28 | 2004-07-29 | 2005-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-28 | 2008-07-29 | 2009-01-28 | $7700.00 | Window Closed / Lapsed |