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US5597756A
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Process for fabricating a cup-shaped DRAM capacitor using a multi-layer partly-sacrificial stack
Assignee: Micron Technology Inc
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Filing: 1995-06-21
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Granted: 1997-01-28
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Expires: 2015-06-21
Abstract
Abstract This invention is a process for fabricating a dynamic random access memory (DRAM) having a stacked capacitor with hemispherical-grain (HSG) polysilicon asperities on an amorphous silicon storage-node plate. The process enables the selective formation of HSG polysilicon asperities on the storage-node plates and a subsequent deposition of a high-quality silicon nitride cell dielectric layer on the asperity-covered storage-node plates. The process is preferably initiated following field oxide formation, wordline formation, access transistor source/drain region formation, deposition of a planarizing dielectric layer, formation of bitline contact and storage-node contact openings in the planarizing layer, and formation of conductive plugs in both types of contact openings. The process is implemented by sequentially depositing a first tetraethylorthosilicate (TEOS) oxide layer, a first silicon nitride layer, a second TEOS oxide layer, a second silicon nitride layer, and a boro-phospho-silicate glass (BPSG) layer to form a multi-layer partly-sacrificial stack. Depressions are etched in the partly-sacrificial stack and amorphous silicon cup-shaped storage-node plates are formed in the depressions. Following removal of the BPSG layer and the second silicon nitride layer, HSG polysilicon asperities are formed on the plates. The second TEOS oxide layer is then removed, exposing the first silicon nitride layer. A silicon nitride cell dielectric layer is then deposited over the surface of the array.
Inventors
- 👤 Pierre C. Fazan
- 👤 Thomas A. Figura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 06:28
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10B12/318; Y; Y10; Y10S; Y10S438/00; Y10S438/964
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
155 words
A method of forming a dynamic random access memory cell capacitor, said method comprising the following steps: (a) providing a silicon substrate having a storage-node junction on an upper surface thereof; (b) depositing alternating layers of silicon dioxide and silicon nitride superjacent the substrate; (c) etching a hole through the alternating layers directly above the storage-node junction; (d) forming a storage-node plate from an amorphous silicon layer which is in electrical communication with the storage-node junction through the hole, and which is in contact with at least an edge of each of said alternating layers; (e) forming HSG polysilicon asperities on only the storage-node plate while one of said silicon dioxide layers is exposed; (f) removing said one of said silicon dioxide layers to expose an underlying silicon nitride layer; (g) forming a cell dielectric layer on the asperity-covered storage-node plate; and (h) depositing a cell plate layer on top of the cell dielectric layer.
Claim 2
Independent Claim
155 words
A method of forming a dynamic random access memory cell capacitor, said method comprising the following steps: (a) providing a silicon substrate having a storage-node junction on an upper surface thereof; (b) depositing alternating layers of silicon dioxide and silicon nitride superjacent the substrate; (c) etching a hole through the alternating layers directly above the storage-node junction; (d) forming a storage-node plate from an amorphous silicon layer which is in electrical communication with the storage-node junction through the hole, and which is in contact with at least an edge of each of said alternating layers; (e) forming HSG polysilicon asperities on only the storage-node plate while one of said silicon dioxide layers is exposed; (f) removing said one of said silicon dioxide layers to expose an underlying silicon nitride layer; (g) forming a cell dielectric layer on the asperity-covered storage-node plate; and (h) depositing a cell plate layer on top of the cell dielectric layer.
Claim 3
Dependent Claim
46 words
The method of claim 1, which further comprises the step of providing a base dielectric layer between the substrate and the alternating layers, the base dielectric layer having a vertically-oriented conductive plug which extends through the base dielectric layer and makes contact with the storage-node junction.
Claim 4
Dependent Claim
15 words
The method of claim 2, wherein the base dielectric layer is formed from borophosphosilicate glass.
Claim 5
Dependent Claim
57 words
The method of claim 1, wherein etching of the hole through the alternating layers occurs during the following sequence of steps which commence following step (b) of claim 1: (a) depositing a mold layer superjacent the alternating layers; and (b) forming a depression which penetrates the mold layer and all alternating silicon dioxide and silicon nitride layers.
Claim 6
Dependent Claim
23 words
The method of claim 4, wherein the mold layer is formed from borophosphosilicate glass, said mold layer being reflowed after it is deposited.
Claim 7
Dependent Claim
86 words
The process of claim 4, wherein the uppermost of said alternating layers is silicon nitride, and formation of the storage-node plate comprises the following sequence of steps: (a) depositing an amorphous silicon layer which lines the depression and covers an upper surface of the mold layer; (b) removing a portion of the amorphous silicon layer which covers the upper surface of the mold layer, thus forming a singulated storage-node plate; and (c) removing the mold layer so as to expose the uppermost of said alternating layers.
Claim 8
Dependent Claim
15 words
The method of claim 1 wherein the uppermost of said alternating layers is silicon dioxide.
Claim 9
Dependent Claim
14 words
The method of claim 1, wherein the silicon dioxide layers are formed from tetraethylorthosilicate.
Claim 10
Dependent Claim
19 words
The method of claim 1, wherein the alternating layers comprise two silicon nitride layers and one silicon dioxide layer.
Claim 11
Dependent Claim
19 words
The method of claim 2, wherein the alternating layers comprise two silicon nitride layers and two silicon dioxide layers.
Claim 12
Dependent Claim
29 words
The method of claim 10, wherein one of the two silicon dioxide layers functions as a buffer layer between the base dielectric layer and a superjacent silicon nitride layer.
Claim 13
Dependent Claim
12 words
The method of claim 1, wherein said cell dielectric comprises silicon nitride.
Claim 14
Dependent Claim
15 words
The method of claim 1 wherein said cell dielectric is deposited via chemical vapor deposition.
Claim 15
Dependent Claim
14 words
The method of claim 4, wherein said depression is formed with a plasma etch.
Claim 16
Dependent Claim
15 words
The method of claim 6, wherein the mold layer is removed with a wet etch.
Claim 17
Dependent Claim
20 words
The method of claim 1, wherein the HSG polysilicon asperities are formed on the storage-node plate with a seeding process.
Claim 18
Dependent Claim
20 words
The method of claim 1, wherein the HSG polysilicon asperities are formed on the storage-node plate with an annealing process.
Claim 19
Dependent Claim
27 words
The method of claim 1, wherein the HSG polysilicon asperities are formed on the storage-node plate via a combination of a seeding process and an anneal process.
Claim 20
Independent Claim
259 words
A method of forming a dynamic random access memory cell capacitor comprising the following steps: (a) providing a base dielectric layer through which a vertically oriented polysilicon plug makes contact to a subjacent storage-node junction of a memory cell access device; (b) depositing a first silicon nitride layer superjacent the base dielectric layer; (c) depositing a silicon dioxide layer on top of the first silicon nitride layer; (d) depositing a second silicon nitride layer on top of the silicon dioxide layer; (e) depositing a mold layer on top of the second silicon nitride layer; (f) forming a depression in the mold layer and all intervening layers between the mold layer and the base dielectric layer, such that said depression exposes at least an upper surface of the polysilicon plug; (g) depositing an amorphous silicon layer which lines the depression, which is in direct contact with said polysilicon plug, and which covers an upper surface of the mold layer; (h) removing a portion of the amorphous silicon layer which covers the upper surface of the mold layer, thus forming a singulated storage-node plate; (i) removing the mold layer so as to expose the second silicon nitride layer; (j) removing the second silicon nitride layer to expose the silicon dioxide layer; (k) forming HSG polysilicon asperities on only the storage-node plate; (l) removing the silicon dioxide layer so as to expose the first silicon nitride layer; (m) depositing a cell dielectric layer on the asperity-covered storage-node plate; and (n) depositing a cell plate layer on top of the cell dielectric layer.
Claim 21
Independent Claim
259 words
A method of forming a dynamic random access memory cell capacitor comprising the following steps: (a) providing a base dielectric layer through which a vertically oriented polysilicon plug makes contact to a subjacent storage-node junction of a memory cell access device; (b) depositing a first silicon nitride layer superjacent the base dielectric layer; (c) depositing a silicon dioxide layer on top of the first silicon nitride layer; (d) depositing a second silicon nitride layer on top of the silicon dioxide layer; (e) depositing a mold layer on top of the second silicon nitride layer; (f) forming a depression in the mold layer and all intervening layers between the mold layer and the base dielectric layer, such that said depression exposes at least an upper surface of the polysilicon plug; (g) depositing an amorphous silicon layer which lines the depression, which is in direct contact with said polysilicon plug, and which covers an upper surface of the mold layer; (h) removing a portion of the amorphous silicon layer which covers the upper surface of the mold layer, thus forming a singulated storage-node plate; (i) removing the mold layer so as to expose the second silicon nitride layer; (j) removing the second silicon nitride layer to expose the silicon dioxide layer; (k) forming HSG polysilicon asperities on only the storage-node plate; (l) removing the silicon dioxide layer so as to expose the first silicon nitride layer; (m) depositing a cell dielectric layer on the asperity-covered storage-node plate; and (n) depositing a cell plate layer on top of the cell dielectric layer.
Claim 22
Dependent Claim
20 words
The method of claim 19, wherein the base dielectric layer and the mold layer are both formed from borophosphosilicate glass.
Claim 23
Dependent Claim
26 words
The process of claim 19, which further comprises the step of depositing a buffer layer between the base dielectric layer and the first silicon nitride layer.
Claim 24
Dependent Claim
18 words
The process of claim 19, wherein said silicon dioxide layer and said buffer layer are formed from tetraethylorthosilicate.
Claim 25
Dependent Claim
14 words
The method of claim 19, wherein said depression is formed with a plasma etch.
Claim 26
Dependent Claim
15 words
The method of claim 19, wherein the mold layer is removed with a wet etch.
Claim 27
Dependent Claim
20 words
The method of claim 19, wherein the HSG polysilicon asperities are formed on the storage-node plate via an seeding process.
Claim 28
Dependent Claim
20 words
The method of claim 19, wherein the HSG polysilicon asperities are formed on the storage-node plate via a seeding process.
Claim 29
Dependent Claim
27 words
The method of claim 19, wherein the HSG polysilicon asperities are formed on the storage-node plate via a combination of a seeding process and an anneal process.
Claim 30
Dependent Claim
13 words
The method of claim 19, wherein the deposited silicon layer is amorphous silicon.
Claim 31
Dependent Claim
13 words
The method of claim 19, wherein the cell dielectric layer comprises silicon nitride.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-28 | 2000-07-29 | 2001-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-28 | 2004-07-29 | 2005-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-28 | 2008-07-29 | 2009-01-28 | $7700.00 | Window Closed / Lapsed |