Patent US1819103A successfully refreshed from Google Patents.
Patent US5593903A successfully refreshed from Google Patents.
US5593903A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming contact pads for wafer level testing and burn-in of semiconductor dice
Assignee: NXP USA Inc
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Filing: 1996-03-04
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Granted: 1997-01-14
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Expires: 2016-03-04
Abstract
Abstract A method of forming contact pads (140) that allows for wafer level testing and burn-in of semiconductor die (22). A plurality of semiconductor die (22) are formed upon a semiconductor wafer (20), each semiconductor die (22) having a plurality of bonding pads (78). A contact pad (140) is formed overlying each bonding pad (78) and is electrically coupled to the bonding pad (78) and to wafer test pads (38) through vertical and/or horizontal wafer conductors (42-47 and 52-53 respectively) so that each semiconductor die (22) is uniquely identified. Contact pads (140) protect underlying bonding pads (78) during the formation and removal of vertical and/or horizontal wafer conductors (42-47 and 52-53 respectively). Thus, wafer level electrical testing and/or burn-in can be performed prior to designating a final packaging method for the semiconductor die (22).
Inventors
- 👤 William M. Beckenbaugh
- 👤 William H. Lytle
- 👤 Bernard Berman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:31
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2884; H; H10; H10W; H10W72/00; H10W72/01; H10W72/019; G01R31/282; G01R31/2831; H10W72/90; H10W72/921; H10W72/923; H10W72/951; H10W72/952
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
115 words
A method for forming contact pads for wafer level testing of integrated circuit die comprising the steps of: providing a semiconductor substrate having a plurality of integrated circuit die formed thereon, wherein each integrated circuit die has a plurality of bonding pads; forming a conductive etch-barrier layer overlying and electrically coupled to the plurality of bonding pads; and forming a conductive layer overlying the conductive etch-barrier layer, wherein the conductive layer is electrically coupled to the plurality of bonding pads, and whereby the conductive etch-barrier layer protects the plurality of bonding pads when the conductive layer is patterned and etched to form a contact pad overlying at least one of the plurality of bonding pads.
Claim 2
Independent Claim
115 words
A method for forming contact pads for wafer level testing of integrated circuit die comprising the steps of: providing a semiconductor substrate having a plurality of integrated circuit die formed thereon, wherein each integrated circuit die has a plurality of bonding pads; forming a conductive etch-barrier layer overlying and electrically coupled to the plurality of bonding pads; and forming a conductive layer overlying the conductive etch-barrier layer, wherein the conductive layer is electrically coupled to the plurality of bonding pads, and whereby the conductive etch-barrier layer protects the plurality of bonding pads when the conductive layer is patterned and etched to form a contact pad overlying at least one of the plurality of bonding pads.
Claim 3
Dependent Claim
42 words
The method of claim 1, wherein the step of providing a semiconductor substrate further comprises forming an opening in a passivation layer wherein each of the plurality of bonding pads extends to an upper surface of the semiconductor substrate through said opening.
Claim 4
Dependent Claim
26 words
The method of claim 1, wherein the step of providing a semiconductor substrate further comprises forming the plurality of bonding pads from a metal comprising aluminum.
Claim 5
Dependent Claim
25 words
The method of claim 1, wherein the step of forming a conductive etch-barrier layer further comprises forming the conductive etch-barrier layer from a titanium-tungsten alloy.
Claim 6
Dependent Claim
28 words
The method of claim 1, wherein the step of forming a conductive layer further comprises forming the second conductive layer from a metal comprised of aluminum or copper.
Claim 7
Dependent Claim
38 words
The method of claim 1, further comprising the steps of: patterning the conductive layer by etching to expose portions of the conductive etch-barrier layer; and removing exposed portions of the conductive etch-barrier layer to form the contact pads.
Claim 8
Dependent Claim
56 words
The method of claim 6, wherein the step of patterning the conductive layer further comprises forming a pattern that includes a plurality of wafer test pads at a periphery of the semiconductor substrate, wherein the plurality of wafer test pads are electrically coupled to the contact pads such that each integrated circuit die is uniquely identified.
Claim 9
Dependent Claim
23 words
The method of claim 7, further comprising the step of performing a wafer level electrical test of the plurality of integrated circuit die.
Claim 10
Dependent Claim
21 words
The method of claim 8, wherein the step of performing a wafer level electrical test further comprises a wafer level burn-in.
Claim 11
Dependent Claim
41 words
The method of claim 6, further comprising the steps of: removing the conductive layer; removing the conductive etch-barrier layer; and singulating the plurality of integrated circuit die, wherein each integrated circuit die is suitable for wire bonding or forming conductive bumps.
Claim 12
Dependent Claim
53 words
The method of claim 6, further comprising the steps of: removing the conductive layer; removing portions of the conductive etch-barrier layer not overlying the bonding pads; forming conductive bumps overlying the conductive etch-barrier layer, wherein said conductive bumps are electrically coupled to the bonding pads; and singulating the plurality of integrated circuit die.
Claim 13
Dependent Claim
65 words
The method of claim 6, further comprising the steps of: removing portions of the conductive layer and the conductive etch-barrier layer, wherein unremoved portions of the conductive layer and the conductive etch-barrier layer overlie the plurality of bonding pads; forming conductive bumps overlying the conductive layer, wherein said conductive bumps are electrically coupled to the bonding pads; and singulating the plurality of integrated circuit die.
Claim 14
Independent Claim
139 words
A method of manufacturing integrated circuit die that have been tested at the wafer level comprising the steps of: providing a semiconductor substrate having a plurality of integrated circuit die formed thereon, wherein each integrated circuit die has a plurality of bonding pads extending to an upper surface of the semiconductor substrate; forming a etch-barrier layer overlying the upper surface, wherein the etch-barrier layer is electrically coupled to the plurality of bonding pads; forming a conductive layer overlying the etch-barrier layer, wherein the conductive layer is electrically coupled to the plurality of bonding pads; patterning the conductive layer and the etch-barrier layer such that each integrated circuit die is uniquely electrically coupled; electrically testing the plurality of integrated circuit die; removing at least a portion of the conductive layer; and removing at least a portion of the etch-barrier layer.
Claim 15
Independent Claim
139 words
A method of manufacturing integrated circuit die that have been tested at the wafer level comprising the steps of: providing a semiconductor substrate having a plurality of integrated circuit die formed thereon, wherein each integrated circuit die has a plurality of bonding pads extending to an upper surface of the semiconductor substrate; forming a etch-barrier layer overlying the upper surface, wherein the etch-barrier layer is electrically coupled to the plurality of bonding pads; forming a conductive layer overlying the etch-barrier layer, wherein the conductive layer is electrically coupled to the plurality of bonding pads; patterning the conductive layer and the etch-barrier layer such that each integrated circuit die is uniquely electrically coupled; electrically testing the plurality of integrated circuit die; removing at least a portion of the conductive layer; and removing at least a portion of the etch-barrier layer.
Claim 16
Dependent Claim
27 words
The method as in claim 13, wherein the step of patterning the conductive layer and the etch-barrier layer further comprises forming a plurality of wafer test pads.
Claim 17
Dependent Claim
32 words
The method as in claim 14, wherein the step of forming a plurality of wafer test pads further comprises forming the wafer test pads at a peripheral edge of the upper surface.
Claim 18
Dependent Claim
24 words
The method as in claim 13, wherein the step of electrically testing the plurality of integrated circuit die further comprises performing an electrical burn-in.
Claim 19
Dependent Claim
33 words
The method as in claim 13, wherein the step of electrically testing the plurality of integrated circuit die, further comprises performing a functionality test for each of the plurality of integrated circuit die.
Claim 20
Dependent Claim
70 words
The method as in claim 13, wherein the step of patterning the conductive layer and the etch-barrier layer, further comprises the steps of: depositing and patterning a layer of photoresist to expose selected portions of the conductive layer; removing selected portions of the conductive layer to expose portions of the etch-barrier layer; and removing exposed portions of the etch-barrier layer, wherein remaining portions of the conductive layer are essentially unperturbed.
Claim 21
Dependent Claim
66 words
The method as in claim 13, wherein the step of removing at least a portion of the conductive layer, further comprises the steps of: depositing a layer of photoresist over the conductive layer; patterning the layer of photoresist to protect portions of the conductive layer overlying the plurality of bonding pads; and etching unprotected portions of the conductive layer to expose portions of the etch-barrier layer.
Claim 22
Dependent Claim
23 words
The method as in claim 13, wherein the step of forming a conductive layer comprises forming a layer comprised of copper or aluminum.
Claim 23
Dependent Claim
40 words
The method as in claim 13, further comprising the step of forming a plurality of conductive bumps overlying the plurality of bonding pads, wherein each of the plurality of conductive bumps is uniquely electrically coupled to an underlying contact area.
Claim 24
Dependent Claim
20 words
The method as in claim 13, further comprising the step of singulating each of the plurality of integrated circuit die.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-14 | 2000-07-15 | 2001-01-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-14 | 2004-07-15 | 2005-01-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-14 | 2008-07-15 | 2009-01-14 | $7700.00 | Window Closed / Lapsed |