Oscillator for generating a varying amplitude feed forward PFC modulation ramp

Claim 2

An oscillator for use within a power factor correction circuit, comprising: a. means for generating a clock output signal having a frequency, a corresponding period, a first output state and a second output state wherein at a beginning of the period the clock output signal is at the first output state and at an end of the period the clock output signal is at the second output state; b. means for generating a varying amplitude ramp output signal having an increasing state and a decreasing state wherein the means for generating is coupled to receive a full wave rectified alternating current voltage signal from a rectifier; and c. means for synchronizing coupled to the means for generating a clock output signal and to the means for generating a varying amplitude ramp output signal for synchronizing the clock output signal with the varying amplitude ramp output signal so that the varying amplitude ramp output signal is generated with the frequency and the corresponding period.

Claim 3

The oscillator as claimed in claim 1 wherein the ramp output signal is coupled for controlling a switch of a power factor correction circuit.

Claim 4

The oscillator as claimed in claim 1 wherein the means for synchronizing comprises a one-shot circuit having an input coupled to receive the clock output signal and a synchronizing output coupled to the means for generating a varying amplitude ramp output signal and further wherein the synchronizing output has a duty cycle equal to a predetermined percentage of the period.

Claim 5

The oscillator as claimed in claim 3 wherein the means for generating a varying amplitude ramp output signal further includes a first timing resistor and a first timing capacitor coupled to receive the full wave rectified signal and a first discharge transistor coupled to and controlled by the synchronizing output.

Claim 6

The oscillator as claimed in claim 4 wherein the means for generating a varying amplitude ramp output signal further comprises a current mirror circuit coupled between the first timing resistor and the first timing capacitor.

Claim 7

The oscillator as claimed in claim 4 wherein a peak amplitude of the ramp output signal is equal to an amplitude of the full wave rectified signal from the rectifier circuit.

Claim 8

The oscillator as claimed in claim 4 wherein the predetermined percentage is five percent of the period.

Claim 9

An oscillator for generating a clock output signal and a varying amplitude ramp output signal for use within a power factor correction circuit, comprising: a. a clock output signal generating circuit for generating a clock output signal having a frequency, a corresponding period, a first output state and a second output state, wherein the clock output signal is at the first output state at a beginning of the period and at the second output state at an end of the period and wherein the clock output signal generating circuit comprises a second timing resistor, a second timing capacitor and a second discharge transistor and further wherein the clock output signal is coupled for controlling the second discharge transistor; b. a ramp output signal generating circuit including a first timing resistor, a first timing capacitor and a first discharge transistor, for generating a varying amplitude ramp output signal having an increasing state and a decreasing state; and c. a synchronizing circuit coupled to receive the clock output signal from the clock output signal generating circuit and for controlling the first discharge transistor for synchronizing the clock output signal with the varying amplitude ramp output signal so that the varying amplitude ramp output signal also has the frequency and the corresponding period, and further wherein a synchronizing output has a duty cycle equal to a predetermined percentage of the period.

Claim 10

An oscillator for generating a clock output signal and a varying amplitude ramp output signal for use within a power factor correction circuit, comprising: a. a clock output signal generating circuit for generating a clock output signal having a frequency, a corresponding period, a first output state and a second output state, wherein the clock output signal is at the first output state at a beginning of the period and at the second output state at an end of the period and wherein the clock output signal generating circuit comprises a second timing resistor, a second timing capacitor and a second discharge transistor and further wherein the clock output signal is coupled for controlling the second discharge transistor; b. a ramp output signal generating circuit including a first timing resistor, a first timing capacitor and a first discharge transistor, for generating a varying amplitude ramp output signal having an increasing state and a decreasing state; and c. a synchronizing circuit coupled to receive the clock output signal from the clock output signal generating circuit and for controlling the first discharge transistor for synchronizing the clock output signal with the varying amplitude ramp output signal so that the varying amplitude ramp output signal also has the frequency and the corresponding period, and further wherein a synchronizing output has a duty cycle equal to a predetermined percentage of the period.

Claim 11

The oscillator circuit as claimed in claim 8 wherein the ramp output signal generating circuit is coupled to receive a full wave rectified signal from a rectifier circuit having an alternating current voltage signal as its input.

Claim 12

The oscillator circuit as claimed in claim 9 wherein a peak amplitude of the ramp output signal is equal to an amplitude of the full wave rectified signal from the rectifier circuit.

Claim 13

The oscillator circuit as claimed in claim 9 wherein the ramp output signal generating circuit further comprises a current mirror circuit coupled between the first timing resistor and the first timing capacitor.

Claim 14

The oscillator circuit as claimed in claim 9 wherein the predetermined percentage is five percent of the period.

Claim 15

An oscillator for generating a clock output signal and a varying amplitude ramp output signal for use within a power factor correction circuit, comprising: a. a first timing resistor having a first terminal and a second terminal, the first terminal of the first timing resistor coupled to a power supply; b. a first timing capacitor having a first terminal and a second terminal, the first terminal of the first timing capacitor coupled to the second terminal of the first timing resistor forming a timing ramp node and the second terminal of the first timing capacitor coupled to a ground; c. a voltage divider network including a first resistor, a second resistor and a third resistor each having a first terminal and a second terminal, the first terminal of the first resistor coupled to the power supply, the second terminal of the first resistor coupled to the first terminal of the second resistor forming a high threshold node, the second terminal of the second resistor coupled to the first terminal of the third resistor forming a low threshold voltage node and the second terminal of the third resistor coupled to the ground; d. a first discharge resistor having a first terminal and a second terminal, the first terminal of the first discharge resistor coupled to the timing ramp node; e. a first discharge transistor having a base, a collector and an emitter, the collector of the first discharge transistor coupled to the second terminal of the first discharge resistor and the emitter of the first discharge transistor coupled to the ground; f. a first comparator having a negative input, a positive input and an output, the negative input of the first comparator coupled to the high threshold node and the positive input of the first comparator coupled to the timing ramp node; g. a second comparator having a negative input, a positive input and an output, the negative input of the second comparator coupled to the timing ramp node and the positive input of the second comparator coupled to the low threshold node; h. a flip flop having an S input, an R input and a Q output, the S input coupled to the output of the first comparator, the R input coupled to the output of the second comparator and the Q output coupled to the base of the first discharge transistor thereby forming a clock output signal node; i. a voltage rectifier circuit having an input coupled to receive an alternating current voltage signal and an output producing a full wave rectified signal output; j. a second timing resistor having a first terminal and a second terminal, the first terminal of the second timing resistor coupled to the full wave rectified signal output; k. a second timing capacitor having a first terminal and a second terminal, the first terminal of the second timing capacitor coupled to the second terminal of the second timing resistor and the second terminal of the second timing capacitor coupled to the ground; l. a second discharge resistor having a first terminal and a second terminal, the first terminal of the second discharge resistor coupled to the second terminal of the second timing resistor and to the first terminal of the second timing capacitor thereby forming a varying amplitude ramp signal output node; m. a second discharge transistor having a base, a collector and an emitter, the collector of the second discharge transistor coupled to the second terminal of the second discharge resistor and the emitter of the second discharge transistor coupled to the ground; n. a one-shot circuit having an input and an output, the input of the one-shot circuit coupled to the clock output signal node and the output of the one-shot circuit coupled to the base of the second discharge transistor, wherein the one-shot circuit outputs a synchronizing output signal having a duty cycle equal to a predetermined percentage of a period of the clock output signal.

Claim 16

An oscillator for generating a clock output signal and a varying amplitude ramp output signal for use within a power factor correction circuit, comprising: a. a first timing resistor having a first terminal and a second terminal, the first terminal of the first timing resistor coupled to a power supply; b. a first timing capacitor having a first terminal and a second terminal, the first terminal of the first timing capacitor coupled to the second terminal of the first timing resistor forming a timing ramp node and the second terminal of the first timing capacitor coupled to a ground; c. a voltage divider network including a first resistor, a second resistor and a third resistor each having a first terminal and a second terminal, the first terminal of the first resistor coupled to the power supply, the second terminal of the first resistor coupled to the first terminal of the second resistor forming a high threshold node, the second terminal of the second resistor coupled to the first terminal of the third resistor forming a low threshold voltage node and the second terminal of the third resistor coupled to the ground; d. a first discharge resistor having a first terminal and a second terminal, the first terminal of the first discharge resistor coupled to the timing ramp node; e. a first discharge transistor having a base, a collector and an emitter, the collector of the first discharge transistor coupled to the second terminal of the first discharge resistor and the emitter of the first discharge transistor coupled to the ground; f. a first comparator having a negative input, a positive input and an output, the negative input of the first comparator coupled to the high threshold node and the positive input of the first comparator coupled to the timing ramp node; g. a second comparator having a negative input, a positive input and an output, the negative input of the second comparator coupled to the timing ramp node and the positive input of the second comparator coupled to the low threshold node; h. a flip flop having an S input, an R input and a Q output, the S input coupled to the output of the first comparator, the R input coupled to the output of the second comparator and the Q output coupled to the base of the first discharge transistor thereby forming a clock output signal node; i. a voltage rectifier circuit having an input coupled to receive an alternating current voltage signal and an output producing a full wave rectified signal output; j. a second timing resistor having a first terminal and a second terminal, the first terminal of the second timing resistor coupled to the full wave rectified signal output; k. a second timing capacitor having a first terminal and a second terminal, the first terminal of the second timing capacitor coupled to the second terminal of the second timing resistor and the second terminal of the second timing capacitor coupled to the ground; l. a second discharge resistor having a first terminal and a second terminal, the first terminal of the second discharge resistor coupled to the second terminal of the second timing resistor and to the first terminal of the second timing capacitor thereby forming a varying amplitude ramp signal output node; m. a second discharge transistor having a base, a collector and an emitter, the collector of the second discharge transistor coupled to the second terminal of the second discharge resistor and the emitter of the second discharge transistor coupled to the ground; n. a one-shot circuit having an input and an output, the input of the one-shot circuit coupled to the clock output signal node and the output of the one-shot circuit coupled to the base of the second discharge transistor, wherein the one-shot circuit outputs a synchronizing output signal having a duty cycle equal to a predetermined percentage of a period of the clock output signal.

Claim 17

The oscillator as claimed in claim 13 further comprising a current mirror circuit coupled between the second terminal of the second timing resistor and the first terminal of the second timing capacitor.

Claim 18

A one-shot circuit having an input coupled for receiving a reference signal generated by a first signal generating circuit and an output coupled for controlling a frequency of a generated signal generated by a second signal generating circuit for synchronizing the reference signal and the generated signal, thereby causing the frequency of the generated signal to be equal to a frequency of the reference signal, wherein the output has a duty cycle equal to a predetermined percentage of a corresponding period of the reference signal and wherein the generated signal has an amplitude that is related to an amplitude of a full wave rectified alternating current voltage signal.

Claim 19

A one-shot circuit having an input coupled for receiving a reference signal generated by a first signal generating circuit and an output coupled for controlling a frequency of a generated signal generated by a second signal generating circuit for synchronizing the reference signal and the generated signal, thereby causing the frequency of the generated signal to be equal to a frequency of the reference signal, wherein the output has a duty cycle equal to a predetermined percentage of a corresponding period of the reference signal and wherein the generated signal has an amplitude that is related to an amplitude of a full wave rectified alternating current voltage signal.

Claim 20

A synchronizing circuit used within an oscillator of a power factor correction circuit for synchronizing a first output signal, having a first state, a second state, a first frequency and a first corresponding period, generated by a first output signal generating circuit, with a second output signal, having a second frequency, an amplitude related to an amplitude of a full wave rectified alternating current signal, and a second corresponding period, generated by a second output signal generating circuit, so that the first output signal and the second output signal have an equal frequency and corresponding period, wherein the first output signal is a clock signal and the second output signal is a varying ramp output signal, the synchronizing circuit comprising: a. means for receiving the first output signal; and b. means for transmitting a control output signal having a duty cycle coupled to the means for receiving and to the second output signal generating circuit for controlling the second frequency so that the second frequency is equal to the first frequency, wherein the duty cycle is equal to a predetermined percentage of the first corresponding period.

Claim 21

A synchronizing circuit used within an oscillator of a power factor correction circuit for synchronizing a first output signal, having a first state, a second state, a first frequency and a first corresponding period, generated by a first output signal generating circuit, with a second output signal, having a second frequency, an amplitude related to an amplitude of a full wave rectified alternating current signal, and a second corresponding period, generated by a second output signal generating circuit, so that the first output signal and the second output signal have an equal frequency and corresponding period, wherein the first output signal is a clock signal and the second output signal is a varying ramp output signal, the synchronizing circuit comprising: a. means for receiving the first output signal; and b. means for transmitting a control output signal having a duty cycle coupled to the means for receiving and to the second output signal generating circuit for controlling the second frequency so that the second frequency is equal to the first frequency, wherein the duty cycle is equal to a predetermined percentage of the first corresponding period.

Claim 22

An oscillator, comprising: a. means for generating a clock output signal having a frequency, a corresponding period, a first output state and a second output state wherein at a beginning of the period the clock output signal is at the first output state and at an end of the period the clock output signal is at the second output state; b. means for generating a varying amplitude ramp output signal having an increasing state and a decreasing state wherein the ramp output signal is coupled for controlling a switch of a power factor correction circuit; and c. means for synchronizing coupled to the means for generating a clock output signal and to the means for generating a varying amplitude ramp output signal for synchronizing the clock output signal with the varying amplitude ramp output signal so that the varying amplitude ramp output signal is generated with the frequency and the corresponding period.

Claim 23

An oscillator, comprising: a. means for generating a clock output signal having a frequency, a corresponding period, a first output state and a second output state wherein at a beginning of the period the clock output signal is at the first output state and at an end of the period the clock output signal is at the second output state; b. means for generating a varying amplitude ramp output signal having an increasing state and a decreasing state wherein the ramp output signal is coupled for controlling a switch of a power factor correction circuit; and c. means for synchronizing coupled to the means for generating a clock output signal and to the means for generating a varying amplitude ramp output signal for synchronizing the clock output signal with the varying amplitude ramp output signal so that the varying amplitude ramp output signal is generated with the frequency and the corresponding period.

Claim 24

The oscillator as claimed in claim 17 wherein the means for generating a varying amplitude ramp output signal is coupled to receive a full wave rectified signal from a rectifier circuit having as its input an alternating current voltage signal.

Claim 25

The oscillator as claimed in claim 18 wherein the means for synchronizing comprises a one-shot circuit having an input coupled to receive the clock output signal and a synchronizing output coupled to the means for generating a varying amplitude ramp output signal and further wherein the synchronizing output has a duty cycle equal to a predetermined percentage of the period.

Claim 26

The oscillator as claimed in claim 19 wherein the means for generating a varying amplitude ramp output signal further includes a first timing resistor and a first timing capacitor coupled to receive the full wave rectified signal and a first discharge transistor coupled to and controlled by the synchronizing output.

Claim 27

The oscillator as claimed in claim 20 wherein the means for generating a varying amplitude ramp output signal further comprises a current mirror circuit coupled between the first timing resistor and the first timing capacitor.

Claim 28

The oscillator as claimed in claim 20 wherein a peak amplitude of the ramp output signal is equal to an amplitude of the full wave rectified signal from the rectifier circuit.

Claim 29

The oscillator as claimed in claim 20 wherein the predetermined percentage is five percent of the period.

Claim 30

An oscillator for generating a clock output signal and a varying amplitude ramp output signal, comprising: a. a clock output signal generating circuit for generating a clock output signal having a frequency, a corresponding period, a first output state and a second output state, wherein the clock output signal is at the first output state at a beginning of the period and at the second output state at an end of the period; b. a ramp output signal generating circuit including a first timing resistor, a first timing capacitor and a first discharge transistor, for generating a varying amplitude ramp output signal having an increasing state and a decreasing state wherein the ramp output signal is coupled for controlling a switch of a power factor correction circuit; and c. a synchronizing circuit coupled to receive the clock output signal from the clock output signal generating circuit and for controlling the first discharge transistor for synchronizing the clock output signal with the varying amplitude ramp output signal so that the varying amplitude ramp output signal also has the frequency and the corresponding period, and further wherein a synchronizing output has a duty cycle equal to a predetermined percentage of the period.

Claim 31

An oscillator for generating a clock output signal and a varying amplitude ramp output signal, comprising: a. a clock output signal generating circuit for generating a clock output signal having a frequency, a corresponding period, a first output state and a second output state, wherein the clock output signal is at the first output state at a beginning of the period and at the second output state at an end of the period; b. a ramp output signal generating circuit including a first timing resistor, a first timing capacitor and a first discharge transistor, for generating a varying amplitude ramp output signal having an increasing state and a decreasing state wherein the ramp output signal is coupled for controlling a switch of a power factor correction circuit; and c. a synchronizing circuit coupled to receive the clock output signal from the clock output signal generating circuit and for controlling the first discharge transistor for synchronizing the clock output signal with the varying amplitude ramp output signal so that the varying amplitude ramp output signal also has the frequency and the corresponding period, and further wherein a synchronizing output has a duty cycle equal to a predetermined percentage of the period.

Claim 32

The oscillator circuit as claimed in claim 24 wherein the clock output signal generating circuit further comprises a second timing resistor, a second timing capacitor and a second discharge transistor and further wherein the clock output signal is coupled for controlling the second discharge transistor.

Claim 33

The oscillator circuit as claimed in claim 25 wherein the ramp output signal generating circuit is coupled to receive a full wave rectified signal from a rectifier circuit having an alternating current voltage signal as its input.

Claim 34

The oscillator circuit as claimed in claim 26 wherein a peak amplitude of the ramp output signal is equal to an amplitude of the full wave rectified signal from the rectifier circuit.

Claim 35

The oscillator circuit as claimed in claim 27 wherein the ramp output signal generating circuit further comprises a current mirror circuit coupled between the first timing resistor and the first timing capacitor.

Claim 36

The oscillator circuit as claimed in claim 26 wherein the predetermined percentage is five percent of the period.

Claim 37

A synchronizing circuit for synchronizing a first output signal, having a first state, a second state, a first frequency and a first corresponding period, generated by a first output signal generating circuit, with a second output signal, having a second frequency and a second corresponding period, generated by a second output signal generating circuit, so that the first output signal and the second output signal have an equal frequency and corresponding period, wherein the first output signal is a clock signal and the second output signal is a varying ramp output signal, the synchronizing circuit comprising: a. means for receiving the first output signal; b. means for transmitting a control output signal having a duty cycle coupled to the means for receiving and to the second output signal generating circuit for controlling the second frequency so that the second frequency is equal to the first frequency, wherein the duty cycle is equal to a predetermined percentage of the first corresponding period; and c. means for comparing the second output signal to an error signal for forming a switch control signal, wherein the error signal is representative of a difference between a power factor correction circuit output voltage and a desired output voltage and wherein the switch control signal is coupled to control a switch of the power factor correction circuit.

Claim 38

A synchronizing circuit for synchronizing a first output signal, having a first state, a second state, a first frequency and a first corresponding period, generated by a first output signal generating circuit, with a second output signal, having a second frequency and a second corresponding period, generated by a second output signal generating circuit, so that the first output signal and the second output signal have an equal frequency and corresponding period, wherein the first output signal is a clock signal and the second output signal is a varying ramp output signal, the synchronizing circuit comprising: a. means for receiving the first output signal; b. means for transmitting a control output signal having a duty cycle coupled to the means for receiving and to the second output signal generating circuit for controlling the second frequency so that the second frequency is equal to the first frequency, wherein the duty cycle is equal to a predetermined percentage of the first corresponding period; and c. means for comparing the second output signal to an error signal for forming a switch control signal, wherein the error signal is representative of a difference between a power factor correction circuit output voltage and a desired output voltage and wherein the switch control signal is coupled to control a switch of the power factor correction circuit.