US5592008A
Expired / Lapsed
US
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Semiconductor device and method for forming the same
Assignee: Semiconductor Energy Laboratory Co Ltd
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Filing: 1995-07-19
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Granted: 1997-01-07
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Expires: 2015-07-19
Abstract
Abstract A novel structure of TFT is described. In the structure of TFT, an anodic oxidation film, which is a material composing a gate electrode, is laid at the side of gate electrode. An electrode, which is connected to a source, drain region, is in contact with the upper surface and the side of the source, drain region, and extended on the upper surface of an insulation film which is laid on the gate electrode. In the preparation process of TFT, it can be completed by using only two sheets of mask.
Inventors
- 👤 Shunpei Yamazaki
- 👤 Toshiji Hamatani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 18:26
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/01; H10D86/021; H10D86/0231; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0321; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6737; H10D30/6739; H10D86/40; H10D86/60
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
155 words
A complementary thin film transistor pair comprising: a p-channel thin film transistor and an n-channel thin film transistor formed on an insulating surface of a substrate, (a) said p-channel thin film transistor comprising a first semiconductor layer formed on said surface and having source, drain and channel regions therein; a first gate insulating layer formed on said first semiconductor layer; and a first gate electrode formed on said gate insulating layer, (b) said n-channel thin film transistor comprising a second semiconductor layer formed on said surface and having source, drain and channel regions therein; a second gate insulating layer formed on said second semiconductor layer; and a second gate electrode formed on said second gate insulating layer, wherein at least side surfaces of said gate electrodes are formed with an anodic oxide layer of said gate electrodes, and said source and drain regions are offset from the corresponding gate electrode in each of said transistors.
Claim 2
Dependent Claim
155 words
A complementary thin film transistor pair comprising: a p-channel thin film transistor and an n-channel thin film transistor formed on an insulating surface of a substrate, (a) said p-channel thin film transistor comprising a first semiconductor layer formed on said surface and having source, drain and channel regions therein; a first gate insulating layer formed on said first semiconductor layer; and a first gate electrode formed on said gate insulating layer, (b) said n-channel thin film transistor comprising a second semiconductor layer formed on said surface and having source, drain and channel regions therein; a second gate insulating layer formed on said second semiconductor layer; and a second gate electrode formed on said second gate insulating layer, wherein at least side surfaces of said gate electrodes are formed with an anodic oxide layer of said gate electrodes, and said source and drain regions are offset from the corresponding gate electrode in each of said transistors.
Claim 3
Dependent Claim
44 words
The complementary thin film transistor pair of claim 1 wherein each boundary between the channel region and the source and drain regions is substantially aligned with outer edges of said anodic oxide layer of the gate electrode in each of the thin film transistors.
Claim 4
Dependent Claim
140 words
A complementary thin film transistor pair comprising: first and second thin film transistors formed on a substrate, each transistor having at least a semiconductor layer formed on said substrate, source, drain and channel regions formed within said semiconductor layer and a gate electrode formed over said channel region, where the source and drain regions of said first transistor is doped with both of a p-type conductivity impurity and an n-type conductivity impurity while the source and drain regions of the second transistor is doped with only one of said p-type conductivity impurity and said n-type conductivity impurity, wherein at least side surfaces of said gate electrode are formed with an anodic oxide layer of said gate electrodes, and the source and drain regions in each of said first and second thin film transistors are offset from the corresponding gate electrode.
Claim 5
Dependent Claim
140 words
A complementary thin film transistor pair comprising: first and second thin film transistors formed on a substrate, each transistor having at least a semiconductor layer formed on said substrate, source, drain and channel regions formed within said semiconductor layer and a gate electrode formed over said channel region, where the source and drain regions of said first transistor is doped with both of a p-type conductivity impurity and an n-type conductivity impurity while the source and drain regions of the second transistor is doped with only one of said p-type conductivity impurity and said n-type conductivity impurity, wherein at least side surfaces of said gate electrode are formed with an anodic oxide layer of said gate electrodes, and the source and drain regions in each of said first and second thin film transistors are offset from the corresponding gate electrode.
Claim 6
Dependent Claim
44 words
The complementary thin film transistor pair of claim 3 wherein each boundary between the channel region and the source and drain regions is substantially aligned with outer edges of said anodic oxide layer of the gate electrode in each of the thin film transistors.
Claim 7
Dependent Claim
59 words
The complementary thin film transistor pair of claim 3 wherein the concentration of said one of the p-type conductivity impurity and the n-type conductivity impurity contained in the source and drain regions of the second transistor is smaller than the concentration of the other one of the impurity contained in the source and drain regions of the first transistor.
Claim 8
Dependent Claim
152 words
An electro-optical device comprising: a p-channel thin film transistor and an n-channel thin film transistor formed on an insulating surface of a substrate, (a) said p-channel thin film transistor comprising a first semiconductor layer formed on said surface and having source, drain and channel regions therein; a first gate insulating layer formed on said first semiconductor layer; and a first gate electrode formed on said gate insulating layer, (b) said n-channel thin film transistor comprising a second semiconductor layer formed on said surface and having source, drain and channel regions therein; a second gate insulating layer formed on said second semiconductor layer; and a second gate electrode formed on said second gate insulating layer, wherein at least side surfaces of said gate electrodes are formed with an anodic oxide layer of said gate electrodes, and said source and drain regions are offset from the corresponding gate electrode in each of said transistors.
Claim 9
Dependent Claim
152 words
An electro-optical device comprising: a p-channel thin film transistor and an n-channel thin film transistor formed on an insulating surface of a substrate, (a) said p-channel thin film transistor comprising a first semiconductor layer formed on said surface and having source, drain and channel regions therein; a first gate insulating layer formed on said first semiconductor layer; and a first gate electrode formed on said gate insulating layer, (b) said n-channel thin film transistor comprising a second semiconductor layer formed on said surface and having source, drain and channel regions therein; a second gate insulating layer formed on said second semiconductor layer; and a second gate electrode formed on said second gate insulating layer, wherein at least side surfaces of said gate electrodes are formed with an anodic oxide layer of said gate electrodes, and said source and drain regions are offset from the corresponding gate electrode in each of said transistors.
Claim 10
Dependent Claim
13 words
The device of claim 6 wherein said device is a liquid crystal device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-07 | 2000-07-08 | 2001-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-07 | 2004-07-08 | 2005-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-07 | 2008-07-08 | 2009-01-07 | $7700.00 | Window Closed / Lapsed |